WB_SDCARD - Accessible Internal Registers

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Modified by Admin on Sep 13, 2017
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The following sections detail the internal registers for the WB_SDCARD that can be accessed from the host processor.

Data Register for 8-bit Transfers (DATA8)

Address: 000

Access: Read/Write

Value after Reset: Undetermined

This is not actually a register in the true sense of the word, but rather is a single address that is used to access the Transmit and Receive Data registers (TX_DATA and RX_DATA respectively) when performing 8-bit data transfers.

Performing a Wishbone Write to the DATA8 address loads data directly into the TX_DATA register, for subsequent transmission on the SD_CMD line to the SD Card. Performing a Wishbone Read from the DATA8 address retrieves data directly from the RX_DATA register, which contains data received on the SD_DAT0 line from the last completed transfer.

Data Register for 16-bit Transfers (DATA16)

Address: 001

Access: Read/Write

Value after Reset: Undetermined

This is not actually a register in the true sense of the word, but rather is a single address that is used to access the Transmit and Receive Data registers (TX_DATA and RX_DATA respectively) when performing 16-bit data transfers.

Performing a Wishbone Write to the DATA16 address loads data directly into the TX_DATA register, for subsequent transmission on the SD_CMD line to the SD Card. Performing a Wishbone Read from the DATA16 address retrieves data directly from the RX_DATA register, which contains data received on the SD_DAT0 line from the last completed transfer.

How the data word is organized for transmission (and conversely read back upon reception) depends on the state of the endian bit in the Control register (CTRL.5). If this bit is '1' the Controller assumes a 16-bit word has come from/going to a Big Endian processor, in which case:
 
For transmission

DAT_I(15..0) is loaded into TX_DATA(31..16)
 
For reception

RX_DATA(15..0) is presented on DAT_O(15..0)
DAT_O(31..16) are all zeroes.
 
Otherwise, if '0', a Little Endian processor is assumed, in which case:
 
For transmission

DAT_I(7..0) is loaded into TX_DATA(31..24)
DAT_I(15..8) is loaded into TX_DATA(23..16)
 
For reception

RX_DATA(7..0) is presented on DAT_O(15..8)
RX_DATA(15..8) is presented on DAT_O(7..0)
DAT_O(31..16) are all zeroes

Data Register for 32-bit Transfers (DATA32)

Address: 010

Access: Read/Write

Value after Reset: Undetermined

This is not actually a register in the true sense of the word, but rather is a single address that is used to access the Transmit and Receive Data registers (TX_DATA and RX_DATA respectively) when performing 32-bit data transfers.

Performing a Wishbone Write to the DATA32 address loads data directly into the TX_DATA register, for subsequent transmission on the SD_CMD line to the SD Card. Performing a Wishbone Read from the DATA32 address retrieves data directly from the RX_DATA register, which contains data received on the SD_DAT0 line from the last completed transfer.

How the data word is organized for transmission (and conversely read back upon reception) depends on the state of the endian bit in the Control register (CTRL.5). If this bit is '1' the Controller assumes a 32-bit word has come from/going to a Big Endian processor, in which case:
 
For transmission

DAT_I(31..0) is loaded into TX_DATA(31..0)
 
For reception

RX_DATA(31..0) is presented on DAT_O(31..0)
 
Otherwise, if '0', a Little Endian processor is assumed, in which case:
 
For transmission

DAT_I(7..0) is loaded into TX_DATA(31..24)
DAT_I(15..8) is loaded into TX_DATA(23..16)
DAT_I(23..16) is loaded into TX_DATA(15..8)
DAT_I(31..24) is loaded into TX_DATA(7..0)
 
For reception

RX_DATA(7..0) is presented on DAT_O(31..24)
RX_DATA(15..8) is presented on DAT_O(23..16)
RX_DATA(23..16) is presented on DAT_O(15..8)
RX_DATA(31..24) is presented on DAT_O(7..0)

Control Register (CTRL)

Address: 011

Access: Read/Write

Value after Reset: 0000_0022h

This register is used to control aspects of the Controller's operation.

Table 1. The CTRL register.
MSB                                                                                                                                                                                                                LSB
31                                                                                                                                                            6
5
4
3
2
1
0
-
endian
cpha
cpol
-
cs
-


Table 2. The CTRL register bit functions.
Bit
Symbol
Function

CTRL.31..CTRL.6

-

Not Used.

CTRL.5

endian

Endian bit. Use this bit to control the order in which bytes are sent for 16- and 32-bit transfers:

0 – Little Endian Mode. The bits of the least significant byte are sent first
1 – Big Endian Mode. The bits of the most significant byte are sent first

CTRL.4

cpha

SD Clock Phase Control bit. Use this bit to determine the phase of the SD_CLK signal in relation to the transmitted data on the SD_CMD line:

0 – Data is latched on the leading edge and changed on the trailing edge
1 – Data is changed on the leading edge and latched on the trailing edge

CTRL.3

cpol

SD Clock Parity Control bit. Use this bit to determine the idle (inactive) state for the SD_CLK signal:

0 – SD_CLK signal is inactive Low
1 – SD_CLK signal is inactive High

CTRL.2

-

Not Used.

CTRL.1

cs

Chip Select Control bit. This bit is connected through to the WB_SDCARD's SD_DAT3 pin. Use this bit to enable/disable communications with the SD Card:

0 – Enable the SD Card's chip select line
1 – Disable the SD Card's chip select line

CTRL.0

-

Not Used.


All unused bits are ignored when writing to the register and will return '0' when read.

Status Register (STATUS)

Address: 100

Access: Read only

Value after Reset: 0000_0000h

This register is used to determine the current state of the Controller.

Table 3. The STATUS register.
MSB                                                                                                                                                                                                                LSB
31                                                                                                                                                                                                            1
0
-
busy


Table 4. The STATUS register bit functions.
Bit
Symbol
Function

STATUS.31..STATUS.1

-

Not Used.

STATUS.0

busy

Controller Busy Status flag. This bit is set whenever the Controller has started transmitting data to the SD Card (i.e. FSM has left the IDLE state).


All unused bits will return '0' when read.

Clock Divisor Register (CDIV)

Address: 101

Access: Read/Write

Value after Reset: 0000_0000h

This register is used to store a 16-bit divisor for use in generation of the SD_CLK signal, based on the external clock signal (CLK_I), as summarized by the following expression:

SD_CLK = (CLK_I / 2) / CDIV

As part of the SD Clock Generation Unit, an internal counter is used to count up to the value written to the CDIV register. The next edge of SD_CLK will only be generated when the internal counter reaches this divisor value.

The value written to the Clock Divisor register can be anywhere in the valid range 2 16 - 1.

Table 5. The CDIV register.
MSB                                                                                                                                                                                                                LSB
31                                                                                                      16 15                                                                                                      0
-
clock_divisor


The Clock Divisor register must be initialized with a value after a reset – the SD_CLK signal will not be generated if this register is left with the value 0000_0000h.


All unused bits are ignored when writing to the register and will return '0' when read.

Card Detection Register (CARD_DET)

Address: 110

Access: Read Only

Value after Reset: 0000_000Xh

This register is used to determine whether an SD Card has been inserted into the card reader, and the write status of that card.

Table 6. The CARD_DET register.
MSB                                                                                                                                                                                                                LSB
31                                                                                                                                                      8
7
6
5
4
3
2
1
0
-
0
0
0
0
0
0
protect
detect


Table 7. The CARD_DET register bit functions.
Bit
Symbol
Function

CARD_DET.31..CARD_DET.8

-

Not Used.

CARD_DET.7

0

Internally tied to zero.

CARD_DET.6

0

Internally tied to zero.

CARD_DET.5

0

Internally tied to zero.

CARD_DET.4

0

Internally tied to zero.

CARD_DET.3

0

Internally tied to zero.

CARD_DET.2

0

Internally tied to zero.

CARD_DET.1

protect

Write Protection flag. This bit is connected directly to the WB_SDCARD's SD_PROTECT input and is used to flag the write status of the SD Card currently inserted into the SD Card Reader:

0 – The SD Card is Read-only (write protect tab is in the 'locked' position)
1 – The SD Card is writeable (write protect tab is in the 'unlocked' position)

CARD_DET.0

detect

Card Detection flag. This bit is connected directly to the WB_SDCARD's SD_DETECT input and is used to flag whether or not a card is currently inserted into the SD Card Reader:

0 – No SD Card inserted
1 – An SD Card is inserted


All unused bits will return '0' when read.

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