OpenBus Tutorial - Configuring the Clocks, Resets and Interrupts

Management of the clock, reset and interrupt lines for the system are handled in the OpenBus Signal Manager dialog (Tools » OpenBus Signal Manager). These lines are handled separately from the main bus link between devices, to simplify the bus.

We shall use the tabs available in this dialog to now define each of these areas.

1. If you have not already done so, open the OpenBus Signal Manager dialog.
    
2. We shall use a single clock net as input to all applicable devices in the system. On the Clocks tab of the dialog, ensure that the Net to connect to field for each device is set to <Default> and that the Default clock field is set to CLK_I.
    
   
   Figure 1. Configured clock lines for the system.
    
3. We shall also use a single reset net as input to all of the applicable devices in the system. On the Resets tab of the dialog, ensure that the Net to connect to field for each device is set to <Default> and that the Default reset field is set to RST_I.
    
   
   Figure 2. Configured reset lines for the system.
    
4. In the original FPGA design, only the SPI Controller and the VGA Controller are capable of generating interrupts. In both cases, the interrupt lines are not used. We can therefore leave the Interrupts tab of the dialog in its default state, with each individual interrupt line for these two peripheral devices set as Not Connected. The Interrupts tab also lists each of the interrupt pins for the processor, allowing the ability to import interrupts from devices external to the OpenBus System document. As our design has no such external devices, all entries simply remain as Not Exported, meaning that no interrupt lines will be made available on the top-level design schematic.
    
   
   Figure 3. Configured interrupt lines for the system.

Wondering what the final tab of this dialog is for, and why it hasn't been mentioned? The External connection summary tab offers just that – a non-editable listing of all devices and the external interface signals associated to them, and which will be made available on the top-level design schematic.