Analyzing Design Nets

Frozen Content

Modified by Admin on Jan 23, 2014

As part of its LiveDesign methodology, Altium Designer provides you with the ability to analyze nets in an FPGA design, while it is running on the target physical device. Where a design net is connected directly to a pin of the physical device, you have the ability to monitor the status of that pin – in real-time. By using a virtual instrument, such as a logic analyzer, you can gain valuable operational information about your design.

The ability to 'reach in' and interactively analyze design nets can give you the edge needed to finalize development prior to manufacture, leading to shorter time-to-market and making a good product great.

To aid in this analysis, Altium Designer provides the Probe and Instrument Probe directives.

Probe Directive

The days of being able to attach fly-lead probes physically to the pins of a chip and analyze states is fast nearing the doors of antiquity. Devices – especially FPGAs – are becoming pin-saturated beasts which, even if you could 'see' the pins, they are undoubtedly too finely pitched to access externally. So how about monitoring pins from within the design – directly from the schematic sheet? It's a vision made real with LiveDesign and a well-placed Probe directive.

Place a Probe directive on any net (wire or bus) in the design that connects directly to a pin of the physical FPGA device. Once the design has been programmed into the device, the state of such a pin can be monitored, in real-time, directly on the schematic sheet (Figure 1).

Figure 1. FPGA pin status monitoring using Probe directives.

The key to the pin-state display is the directive's ProbeValueDisplay parameter. In fact you could place a Parameter Set directive instead, and as long as this parameter is defined for it, the result would be the same.

For the pin state to be updated in real-time on the schematic, the source FPGA design must be downloaded to the physical FPGA device and the associated JTAG Viewer panel (see Monitoring the State of Device Pins - Live) for that device must be open and remain open.

Instrument Probe Directive

Probing device pins from the schematic is great, but what about being able to analyze and potentially fault-find further back into the design circuitry? No problem. Simply place an Instrument Probe directive, which allows you to monitor any point in a design – not just the status of FPGA device pins. Placed on a net object, such as a wire or bus, it instructs the system to connect the associated net directly to the input of a monitoring instrument (e.g. a logic analyzer) – without having to explicitly wire that net up through the design hierarchy to the sheet with the instrument on it.

In addition, when attached to a net that connects directly to an FPGA device pin, the Instrument Probe directive behaves as per the Probe directive. Again, the JTAG Viewer panel must be open.

The key element that turns this directive from being a simple probe into a powerful point-monitoring aid, is its possession of the additional InstrumentProbe parameter. Once the directive is placed at the point of interest, it is this parameter that is used to effectively 'link' that point to the monitoring device. Simply enter a meaningful name for the probe point – such as the name of the associated net or the particular signal being monitored – then connect a wire to the required input of the monitoring instrument and attach a net label to the wire, the name of which is the same name you have defined for the InstrumentProbe parameter (Figure 2).

Figure 2. Monitoring select points in a design without excessive wiring overhead.

Measurement information obtained through the directive's ProbeValueDisplay parameter is, like the Probe directive, displayed in real-time, over the Hard Devices JTAG chain. In contrast, measurement information obtained through the directive's InstrumentProbe parameter is ONLY displayed after compilation, over the Soft Devices JTAG chain.

A word about probing buses

When an Instrument Probe directive is attached to a bus, the entire bus is taken up to the top-level sheet, irrespective of the name you assign to the InstrumentProbe parameter. When you add a net label to the input for the monitoring instrument, you must define the bus width required.

Consider, for example, having attached an Instrument Probe directive to a bus with identifier Port1_Out[7..0] on a lower-level sheet. The value for the InstrumentProbe parameter could be simply set to Port1_Out. The entire bus will be connected up to the sheet with the monitoring device (e.g. a configurable Logic Analyzer). Should you wish to wire up the whole bus as an input signal to the device, you would place a bus to the required input and add a net label of Port1_Out[7..0]. If you only wanted a particular signal or range of signals from the bus, you can simply define the width required in the attached net label (e.g. Port1_Out[4..2]).