Monitoring the State of Device Pins - Live

Once the design has been downloaded to the FPGA, the Hard Devices JTAG chain can be used to monitor the state of the FPGA pins, in real-time. This is achieved using the device's associated JTAG Viewer panel (accessible from its instrument panel), set to operate in Live Update mode (Figure 1).

Figure 1. Enable the Live Update option in the device's associated JTAG Viewer panel to monitor the state of the FPGA pins in real-time!

Where high-density component packaging makes physical probing of device pins impossible, the JTAG Viewer panel facilitates physical design debugging, 'virtual-style'. It uses the JTAG communications standard to interrogate the state of the pins in any JTAG compliant device in your design, not just the FPGAs. It presents the state of each pin, and includes an image of both the schematic symbol and the footprint, helping you to analyze and debug your design.