WB_PWMX - Host to Controller Communications

Communications between a 32-bit host processor and the WB_PWMX Controller are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible internal registers, see Wishbone Communications - 32-bit Processor to Slave Peripheral.

Notes

1. When writing to the upper 6 bits of the PWMRG register, the value loaded into the register depends on the current resolution mode, determined by the mod1 and mod0 bits in the PWCON register. The following table summarizes how the byte of data from the host processor is used when writing to PWMRG[13..8].
    

   Resolution Mode (mod1:mod0)	Value loaded into PWMRG[13..8]
   00	"000000"
   01	"0000" & DAT_I(1..0)
   10	"00" & DAT_I(3..0)
   11	DAT_I(5..0)

    
2. When reading the upper 6 bits of the PWMRG register, the byte value presented to the host processor is padded with zeros in the most significant 2 bits:
    
   DAT_O <= "00" & PWMRG(13..8)