WB_MULTIMASTER - Pin Description
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Table 1 summarizes the function of each of the pins available for the component. Only the pins for one master interface are listed. The function of each of the pins of the additional master interfaces is identical – only the pin names change with respect to their prefix. By default, the pins for master interface 1 will be prefixed with m1, the pins for master interface 2 with m2, and so on. These default prefixes can be replaced with alternative required naming when configuring the device (see Configuration).
| Name | Type | Polarity/ Bus size | Description |
|---|---|---|---|
| Wishbone Master Interface Signals | |||
| m1_STB_I | I | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| m1_CYC_I | I | High | Cycle signal. When asserted, indicates the start of a valid Wishbone bus cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers |
| m1_ACK_O | O | High | Standard Wishbone device acknowledgement signal. When this signal goes High, the connected Wishbone slave device has finished execution of the requested action and the current bus cycle is terminated |
| m1_ADR_I | I | 0-32 (see note 1) | Standard Wishbone address bus. Used to select an address in the connected Wishbone slave device for writing to/reading from |
| m1_DAT_O | O | 8/16/32 (see note 2) | Data to be sent to the connected Wishbone master device |
| m1_DAT_I | I | 8/16/32 (see note 2) | Data received from the connected Wishbone master device |
| m1_SEL_I | I | 4/High | Select input, used to determine where data is placed on the m0_DAT_O line during a Read cycle and from where on the m0_DAT_I line data is accessed during a Write cycle. Each of the data ports is 32-bits wide with 8-bit granularity, meaning data transfers can be 8-, 16- or 32-bit. The four select bits allow targeting of each of the four active bytes of a port, with bit 0 corresponding to the low byte (7..0) and bit 3 corresponding to the high byte (31..24) |
| m1_WE_I | I | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle. 0 = Read |
| m1_CLK_I | I | Rise | External (system) clock signal |
| m1_RST_I | I | High | External (system) reset signal |
| m1_INT_O | I | 32 | Interrupt signals to be sent to the connected Wishbone master device |
| Wishbone Slave Interface Signals | |||
| STB_O | O | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| CYC_O | O | High | Cycle signal. When asserted, indicates the start of a valid Wishbone bus cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers |
| ACK_I | I | High | Standard Wishbone device acknowledgement signal. When this signal goes High, the connected Wishbone slave device has finished execution of the requested action and the current bus cycle is terminated |
| ADR_O | O | 0-32 (see note 1) | Standard Wishbone address bus. Used to select an address in the connected Wishbone slave device for writing to/reading from |
| DAT_I | I | 8/16/32 (see note 2) | Data received from the connected Wishbone slave device |
| DAT_O | O | 8/16/32 (see note 2) | Data to be sent to the connected Wishbone slave device |
| SEL_O | O | 4/High | Select output, used to determine where data is placed on the DAT_O line during a Write cycle and from where on the DAT_I line data is accessed during a Read cycle. Each of the data ports is 32-bits wide with 8-bit granularity, meaning data transfers can be 8-, 16- or 32-bit. The four select bits allow targeting of each of the four active bytes of a port, with bit 0 corresponding to the low byte (7..0) and bit 3 corresponding to the high byte (31..24) |
| WE_O | O | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle. 0 = Read |
| CLK_O | O | Rise | External (system) clock signal for connection to the CLK_I input of the connected slave device. Though not part of the standard Wishbone interface, this signal is provided for convenience when wiring your design |
| RST_O | O | High | External (system) reset signal for connection to the RST_I input of the connected slave device. Though not part of the standard Wishbone interface, this signal is provided for convenience when wiring your design |
| INT_I | I | 32 | Interrupt signals received from a connected WB_INTERCON |
Notes
- All ADR_I buses and the ADR_O bus are set to the same size, simultaneously, using the Address Bus Width field when configuring the component.
- The size of the data bus (DAT_O and DAT_I) for both master and slave interfaces is determined, simultaneously, by the value entered for the Data Bus Width when configuring the component.