WB_MULTIMASTER - Configuration

The WB_MULTIMASTER component can be configured after placement on the schematic sheet. Simply right-click and choose the command to configure the component from the pop-up menu that appears (e.g. Configure U_MM1 (WB_MULTIMASTER) for a component with designator U_MM1). Alternatively, click on the Configure button, available in the properties dialog for the component.

The Configure (Wishbone MultiMaster) dialog will appear, as shown in Figure 1.

Figure 1. Configuring the Multi-Master peripheral.

Use the dialog to define the following properties for the component as required:

Type

This region of the dialog enables you to specify the way in which the Wishbone Masters contest for the slave resource. The following options are available:

• Round Robin – masters access the slave in sequence, from first (top) to last (bottom).

• Priority – masters access the slave in accordance with a specified order of priority.

Masters

This region of the dialog allows you to specify how many master interfaces the device will have. Between two and eight masters are supported.

Round Robin / Priority Order

The display of this region in the dialog will change to reflect the setting for Type and the number of masters specified. If Type is set to Round Robin, then this region will display as shown in Figure 2. The shared resource will be accessed by each master in turn, from the top of the list down.

Figure 2. Order of access when configured in Round
Robin mode.

Use the Name field to change the prefix for each master from its default (m1, m2, etc) as required. Use the Spaces After Pins field to determine the amount of blank space that is inserted after the bank of pins for that master interface. This allows you to space the master interfaces appropriately, so that each master device can be directly connected to its corresponding interface, without the need for additional external wiring.

If Type is set to Priority, then the region will display as shown in Figure 3.

Figure 3. Order of access when configured in Priority
mode.

As you can see, this simply involves an additional column – Priority. Use this column to determine the order of priority – from Highest (1) to Lowest (8) – for masters to adhere to when accessing the shared resource.

The interface assigned the highest priority is distinguished on the schematic symbol by insertion of the text "High Priority".

Figure 4. Distinguishing the Master
interface that has highest priority.

Master With No Delay

This region of the dialog allows you to specify one master to be granted instant access to the bus when the WB_MULTIMASTER is 'idle'. This reduces latency as the nominated master experiences no delay in acquiring access. Typically, when operating in Priority mode, the master specified here will be the one assigned highest priority.

The interface assigned to be the master with no delay is distinguished on the schematic symbol by insertion of the text "No Delay".

Figure 5. Distinguishing the Master
interface that has instant access.

Address Bus Width

This region of the dialog allows you to specify the number of address bits required to drive the connected slave device. The width chosen is applied to all interfaces of the WB_MULTIMASTER.

When connecting to a single slave memory device – which is connected via the appropriately configured Memory Controller component – you need to set the address bus to the same width as the ADR_I line for the Memory Controller. The Memory Controller will automatically size its ADR_I line according to the size of the physical memory it is connecting to. A Wishbone Interconnect must then be used between the Multi-Master and the processor's External Memory Interface, to handle the address line mapping.

When connecting to a bank of physical memory devices through a Wishbone Interconnect, the address bus must be set to 32 Bits - Range = 4GB, which matches the ADR_I line of the Interconnect's master interface.

When connecting to a single slave peripheral device, you need to set the Multi-Master's address bus to the same width as the ADR_I line for the peripheral. A Wishbone Interconnect must then be used between the Multi-Master and the processor's Peripheral I/O Interface, to handle the address line mapping.

When connecting to a bank of peripheral devices through a Wishbone Interconnect, the address bus must be set to 24 Bits - Range = 16MB, which matches the ADR_I line of the Interconnect's master interface.

Data Bus Width

This region allows you to specify the resolution of the data bus for the slave device being connected. 8-bit, 16-bit and 32-bit data bus widths are supported. The width chosen is applied to all interfaces of the WB_MULTIMASTER.

Interrupts

Enable the Show Interrupt Pins option in this region of the dialog to add the INT_O[31..0] and INT_I[31..0] pins to the master and slave interfaces respectively. The interrupt pins would be added when the Multi-Master component is used to connect multiple 32-bit processors to a bank of peripheral I/O devices, via a Wishbone Interconnect. This provision allows interrupts generated by those peripherals to be passed from the Interconnect through to the processors.