Third Party Boards - Direct Connection using a Third Party Parallel Cable

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Although connection using Altium's USB JTAG Adapter (or through a NanoBoard) is the simplest method of interfacing Altium Designer with your development board, direct connection of a development board to the PC can still be made using the parallel port cable for that board. For example, an Altera Nios Stratix10 board can be connected using the ByteBlaster parallel cable.

If the connecting parallel cable ends in fly leads, connection of the Hard and Soft JTAG chains is quite painless – simply connect the two sets of four JTAG signals to the relevant header pins on the development board. Connect the Hard Devices JTAG chain signals to the relevant pins of the JTAG header on the development board. Connect the Soft Devices JTAG chain signals to the relevant general purpose I/O header, which has four device IO pins available.

If the parallel cable does not end in fly leads, you will need to 'tap-off' the soft signals from the parallel port cable and wire them to the relevant general purpose header.
 

Care must be taken to ensure that the voltage levels of the JTAG signals sent to a physical device are at safe levels for that device. For example, if the physical device has a supply voltage of 2.5V, sending JTAG signals direct from the parallel port (with voltages of 5V) would be too high. In such cases, voltage translation (or shifting) would be required to step the voltage down to required (and safe) operating levels for the FPGA device (see Voltage Shifting)

For a more convenient, streamlined method of connecting your development board, use Altium's USB JTAG Adapter. This device plugs easily into a free USB port on your PC, and delivers Hard and Soft Devices JTAG chain signals conveniently through a flying-lead cable. For more information, see Connection using Altium's USB JTAG Adapter.

Accessing the JTAG Chains

Figure 1 shows the relationship between the software, the Hard and Soft Devices JTAG chains and the FPGA development board.


Figure 1. Accessing information for Hard and Soft Devices chains over the parallel port cable.

To simplify the process of wiring between the parallel port on the PC and the development board, the software supports reprogramming which pins on the parallel port are used to implement the two JTAG chains.

Mapping the JTAG Chains to the Parallel Port Pins

With respect to the Hard Devices JTAG chain, JTAG-compliant development boards will have the JTAG pins on the physical FPGA device routed to an on-board interface connector. Depending on the voltage levels used, it may be possible to connect directly from this connector to the parallel port on the PC. Routing for the Soft Devices JTAG chain may or may not be available on-board.

FPGA development boards are typically designed to work with device vendor software development tools. This means that the specific pins of the parallel port that are used for JTAG signals are designated by the Vendor. So, for example, Altera and Xilinx-based development boards will typically use interface connector pinouts to suit the parallel port pin assignments defined by Altera and Xilinx in their interface cable documentation.

Altera and Xilinx use different pinout specifications. To support direct use of their programming cables Altium Designer supports reprogramming the JTAG pin assignments on the parallel port. This pin assignment (or mapping) is carried out using a JTAG Board file (*.JTGBRD). Multiple files allow you to essentially 'reprogram' the parallel port according to the particular development board currently plugged-in to the system.

Three such files can be found in the \System folder of the software installation, defining mapping for the following board types:

  • Altium NanoBoard (Nanoboard.JTGBRD)
  • Xilinx Development Board (Xilinx.JTGBRD)
  • Altera Development Board (Altera.JTGBRD)

Note: The mappings used in the [HardChannel] section of both the Altera.JTGBRD and Xilinx.JTGBRD files have been set to use the parallel port pins designated by that Vendor. Although not typically supported, mappings in the [SoftChannel] section of the Xilinx.JTGBRD file have been defined ready, as an example. These should be modified according to design requirements.
 

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