Specifying the Device and Mapping the FPGA Pins
Having made the physical connections required to interface your development board to the Altium Designer Software, you can now prepare an FPGA design so it can be programmed into the target FPGA. To do this you need to:
- Specify the target FPGA device.
- Implement the soft JTAG chain and map it to physical pins on the FPGA. These pins will ultimately receive the four signals you have previously wired to the associated general purpose I/O header on the board.
- Map the nets in the design to pins of the physical device.
Specifying the target device and mapping the nets in the FPGA design to pins on the device is done in Constraint files. One or more constraint files can be used to specify implementation information for a design, including:
- The target PCB project
- The target FPGA device
- FPGA net-to-physical device pin assignments
- Pin configuration information, such as output voltage settings
- Design timing constraints, such as allocating a specific net to a special function pin on the device
- FPGA Place and Route constraints
This approach of separating the design source files from the implementation details lets you easily map one design to different device + PCB combinations. Since the FPGA project can have multiple constraint files targeting different implementations, you need some way of configuring when the different constraint files are used. This is done by defining a unique configuration for each target implementation – for each configuration you specify which constraint file(s) to use.
Use the following linked pages to create the constraint file for your board and assign it to a configuration for your FPGA design project.