Assigning Design Nets to Physical Pins of the FPGA Device

Frozen Content

Modified by Admin on Sep 13, 2017

Any net that you wish to connect to a physical pin of the target device must be wired to a port on the top schematic sheet for the FPGA design project. Upon compilation of the design, the top sheet is scanned and all nets that connect to ports are assumed to connect to physical pins on the FPGA.

While the ports themselves are defined on the schematic, mapping to the physical pins they are assigned to is carried out in a constraint file. The pin assignments can be either manually defined or determined by running the place and route tools and importing the resulting assignments back into the constraint file.

To quickly add port assignments to the constraint file, select Design » Import Port Constraints from Project from the Constraint Editor's main menus. A record will be added for each port detected on the top schematic sheet of the FPGA project. The pins are not assigned at this stage.

To manually assign (map) a port to an FPGA pin, simply add the required FPGA_PINNUM constraint to the record for that port. For example, to assign the Soft Devices JTAG signals to pins 202-205 of the physical device, the constraint file entry would appear as shown in Figure 1.

Figure 1. Assignment of Soft Devices JTAG chain connections.

For a clock signal, you may prefer to instruct the place and route tools which ports are to be assigned to clock pins, then let the place and route tool choose from the available clock pins on the target device. For example, to constrain the Soft Devices JTAG clock signal (JTAG_NEXUS_TCK) to an FPGA clock resource, you would use the following entry in the constraint file:

Record=Constraint|TargetKind=Port|TargetId=JTAG_NEXUS_TCK|FPGA_CLOCK=TRUE

Taking this constraint one step further, you could define the frequency to be assigned to this signal, for example:

Record=Constraint|TargetKind=Port|TargetId=JTAG_NEXUS_TCK|FPGA_CLOCK_FREQUENCY=1 Mhz

If you have left pin assignment for the place and route tools, when the place and route process is complete the pin assignments can be imported into the constraint file using the Import Pin File command, from the Constraint Editor's Design menu.