Performing Pin Swapping on the PCB
Having defined the Pin Groups as appropriate and enabled pin swapping for the required components, the actual process of swapping pins can now be performed. With the PCB document active, pin swapping tools are available from the Tools » Pin/Part Swapping sub-menu.
During a pin swap operation, Altium Designer analyses the net assigned to the chosen pin and dynamically reassigns the net on any connected routing as well as the pin. This level of functionality means that partially routed nets and pre-routed multilayer escapes from complex BGA devices can be swapped. Differential pairs can also be swapped, taking advantage of the knowledge about differential pin-pairs on FPGAs.
Automatic pin swapping can be carried out for any or all FPGA components in a document, dependent on whether pin swapping is enabled for those components or not. This functionality is provided courtesy of a powerful automatic Optimizer, invoked using the Automatic Net/Pin Optimizer command.
The Optimizer uses a two-stage process – a Fast optimization pass followed by an Iterative pass. You have control over whether to run the iterative pass, but generally it is a good idea to do so in order to achieve optimum results.
The Optimizer will attempt to find the optimal pin allocations for routing, while obeying the defined Pin Group settings. The total routing length and the number of net crossovers are key factors when routing the PCB, and the optimizer will focus on keeping both the routing length and the number of crossovers down to a minimum.
Figure 1 shows an example of an FPGA device on a PCB, which has been rotated by 180 Degrees to create a chaotic connection pattern.
Figure 1. Connections for an FPGA device before auto-pin swapping.
Figure 2 shows how the automatic Optimizer tool can be used to great effect to obtain an optimized set of pin allocations from which to route. The results of the optimization are presented, prior to committing the update to the PCB.
Figure 2. Connections for the same FPGA device after pin swapping optimization.
For a more hands-on, manually controlled approach, interactive pin swapping functionality is provided. Invoked using the Interactive Pin/Net Swapping and Interactive Differential-Pair Swapping commands, this functionality allows for fine tuning and gives the power to make any number of individual pin swaps – again, in accordance with the Pin Groups already configured. In fact, a sequence of swapping processes might typically be performed. For example, the automatic Optimizer tool may be run initially and then the interactive tool(s) used afterwards to fine tune a couple of out of place nets/pins.
If any FPGA components in the design are linked, due to the design being multi-channel in nature, (e.g. U1_X1, U1_X2), they must be optimized together. When using an interactive pin swapping tool, swapping can not be carried out on the linked component and a dialog will appear alerting you to this fact. For example, if U1_X2 is linked to U1_X1, both components must be optimized together, but interactive pin swapping can only be carried out on U1_X1.