Passing PCB Pin Swap Data to the Linked FPGA Project

Frozen Content

Modified by Admin on Sep 13, 2017

After running the automatic Optimizer and/or interactive pin swapping tools, you will need to propagate the resulting changes on the PCB document through to the linked FPGA project. The first step in doing this is to update the schematic sheet(s) in the PCB project. This is done either by using the standard Update Schematics command from the PCB editor's main Design menu, or by clicking on the PCB-Schematic link (or associated icon) directly in the FPGA Workspace Map dialog.

An Engineering Change Order dialog will appear, listing a series of modifications to be performed on the corresponding FPGA Component schematic document(s), in the PCB project. These modifications will depend on the method used to allow pin swapping on the schematic and can involve:

Removing pins from nets (Adding/Removing Net Labels option)

Adding pins to nets (Adding/Removing Net Labels option)

Moving pins to different nets (Adding/Removing Net Labels option)

Changing pin names (Changing Schematic Pins option).

Figure 1. Execution of ECO to resynchronize the PCB document with the source schematics of the parent project.

Executing the changes will result in the linked FPGA and PCB projects becoming unsynchronized, as indicated by the Schematic-FPGA Project link, in the FPGA Workspace Map dialog, displaying in red (Figure 2).

Figure 2. The linked FPGA and PCB projects are unsynchronized, now that the FPGA component schematic in the PCB project has been updated with the pin swapping data.

Clicking on this link will bring up the Synchronize dialog, with the affected (swapped) pins highlighted in red (Figure 3).

Figure 3. The Synchronize dialog now reflects the differences that exist between the two linked projects.

Click on the Update To FPGA button to push the changes to the FPGA project, or more specifically, the appropriate FPGA Constraint file. The update is performed using an ECO, with the required changes appearing as a series of Change Parameter Value modifications in the Engineering Change Order dialog (Figure 4).

Figure 4. Execution of ECO to resynchronize the FPGA and PCB projects, passing the pin swap data to the relevant constraint file.

With the design changes created through use of the pin swapping tools now passed from the PCB project to the FPGA project, the FPGA Workspace Map dialog will show both projects as now being fully synchronized (Figure 5).

Figure 5. The linked FPGA and PCB projects are again fully synchronized, now that pin swap data has been propagated to the relevant constraint file in the FPGA project.

After pin swapping has been carried out on the PCB, the changes pushed through to the FPGA project and the projects re-synchronized, the Vendor Place & Route tools must be run again (Build stage in the Devices view). This is because the pin swap information has been updated in the constraint file only and now needs to be physically applied to the FPGA device. Running the Place & Route tools again will ensure the new pin assignments are used in an updated FPGA programming file.