PS2_W - Host to Controller Communications

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Modified by Admin on Sep 13, 2017

Communications between a 32-bit host processor and the PS2_W are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible internal registers, see Wishbone Communications - 32-bit Processor to Slave Peripheral.

Table 1 summarizes how the 8-bit data word from the host processor is used by each of the internal registers.

Table 1. Values written to internal registers during a write.

Writing to...	Results in...
WCREG	DAT_I(1) loaded into the Wishbone Control register
WDREG	DAT_I(7..0) loaded into the Wishbone Data register

Table 2 summarizes the 'make-up' of the 8-bit data word that is read back from each register.

Table 2. Values read from internal registers during a read.

Reading from...	Presents (to host processor)...
WCREG	8-bit value from the Wishbone Control register
WDREG	8-bit value from the Wishbone Data register