KEYPADA_W - Host to Controller Communications

Communications between a 32-bit host processor and the KEYPADA_W Controller are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycle involved between Host and Controller for reading from the accessible internal registers, see Wishbone Communications - 32-bit Processor to Slave Peripheral.

Table 1 summarizes the 'make-up' of the 8-bit data that is read back from each register.