Getting Started Tutorial - Capturing the Design

Frozen Content

The first thing we need to do is capture our design within the Altium Designer environment. For our simple design circuit, this will involve adding required components to a schematic sheet and wiring them accordingly. Before we can address the schematic and its contents however, we must create a project. The following sections take you through the steps required to capture our twisted-ring counter design.

Creating the FPGA Project

The basis of every design created in the Altium Designer environment is a project file. For an FPGA design, we need to create a new FPGA project (*.PrjFpg). The project document itself is an ASCII file that stores project information, such as the documents that belong to the project, output settings, compilation settings, error checking settings, and so on.

Let's go ahead and create the FPGA project.

  • Create a new FPGA project using the File » New » Project » FPGA Project command.
  • Right-click on the name for this new project (FPGA_Project1.PrjFpg) in the Projects panel and choose the Save Project command. Save the project in the location of your choice, with the name Simple_Counter.PrjFpg, and in a new folder called Basic FPGA Design Tutorial.

Note: Spaces and/or dashes (-) must not be used in project or document filenames. Doing so will result in synthesis errors during design processing. Underscores (_) should be used instead, to provide readability.

Adding a Schematic Source Document

An FPGA project is hierarchical in nature. Any number of schematic, HDL (VHDL or Verilog) or OpenBus documents can be included, with all descendent sub-files referenced using sheet symbols. One common denominator for all projects however is that they must have a single top-level schematic. This sheet not only contains the ports for the design – which interface directly to pins of the physical FPGA device to which the design is targeted – but also facilitates FPGA-PCB integration within Altium Designer.

We shall explore design hierarchy later in this tutorial. For now, we will simply add a single schematic sheet (our top sheet) to our new FPGA project:

  • Add a new schematic document by right-clicking on the FPGA project entry in the Projects panel and choosing the Add New to Project »
    Schematic command. A blank schematic sheet will open as the active document in the main design window.
  • Save this document (File » Save) with the name Simple_Counter.SchDoc, in the same folder as the parent project.
  • The project itself will appear as modified in the Projects panel. Save the project also (right-click on its name and choose Save Project).

Figure 1. New FPGA project with added source schematic.

Placing Components

Now we have our 'blank schematic canvas' it's time to add-in the required components - those that depict the functionality of the design circuitry, and those that provide the interface with resources found on the Desktop NanoBoard NB2DSK01.

Table 1 identifies the components required in defining the twisted-ring counter circuit. All of these components can be found in the FPGA Generic integrated library (FPGA Generic.IntLib), located in the \Library\Fpga folder of the installation.

Table 1. Design components required in the twisted-ring counter schematic.

Component Name
Quantity Required


J-K Flip-Flop with Asynchronous Clear






Bus Joiner - 8-pin input bus to 8 single pin outputs



2-input OR gate with active Low A and B inputs, (single pin version)



8-bit loadable serial/parallel-in parallel-out bidirectional shift register with clock enable and asynchronous clear (bus version)


Table 2 identifies the design interface components required for our design. These components, commonly referred to as port components (or port-plugins), automatically establish connectivity between the relevant resources on the Desktop NanoBoard and the physical IO pins of the daughter board FPGA device to which our design is targeted. From the design perspective, they depict the extents of the design – the physical pins of the target device to which the signals from the design connect. These port components can be found in the FPGA NB2DSK01 Port-Plugin integrated library (FPGA NB2DSK01 Port-Plugin.IntLib), also located in the \Library\Fpga folder of the installation.

Table 2. Port components required in the twisted-ring counter schematic.

Component Name


This component interfaces to the fixed 20MHz system clock signal on the Desktop NanoBoard. We will use this signal to provide the synchronous clock signal to our flip-flop and shift register logic.


This component interfaces to the DIP-switch on the Desktop NanoBoard. We will use three of these switches to control direction of the counter (Left or Right) and also to stop the counter.


This component interfaces to the user LEDs on the Desktop NanoBoard. We will use the LEDs to visually display the output of our counter.


This component interfaces to the 'DAUGHTER BD TEST/RESET' button (push button switch SW7) on the Desktop NanoBoard. We will use this signal (inverted) as a control input to the Load Enable pin of the shift register. As we will tie the D inputs of this register to GND, pressing this button will load '0' into the register's data outputs.

Go ahead and place all of these components on the schematic sheet, as shown in Figure 2. Both of the integrated libraries are installed and available from the Libraries panel by default, so there is no need to add any libraries for this tutorial. Simply make the relevant library active in the panel, select the component entry in the list and either click the Place button at the top-right of the panel, or click and drag the component directly onto the sheet. Schematic placement controls, such as flipping and rotating, allow for fine tuning as needed.

Once placed, finalize the designation of each component using the Tools » Annotate Schematics Quietly command.

Figure 3. Initial placement of components on the schematic sheet, Simple_Counter.SchDoc.

Wiring the Design

Now all components have been placed it is time to wire them all together – adding the connectivity to the design.

  • Go ahead and wire the design initially, as shown in Figure 3, by using the Place » Wire and Place » Bus commands (these commands are also available from the Wiring toolbar, using the and buttons respectively).

Figure 3. Initial wiring - placement of wires and buses.

  • From the Wiring toolbar, click the button to place a GND Power Port. While the port is still floating on the cursor, press the Tab key. From the Power Port dialog that appears, change the Style property to Bar. Now place the port so that it connects to the bottom-left of the wire connecting the CLR pins of the two flip-flops.

Figure 4. Tying flip-flop CLR signals to GND.

  • Now place another GND Power Port – again using the Bar style – so that it connects to the CLR pin of the shift register.
  • From the Wiring toolbar, click the button to place a GND Bus Power Port. Again, change the port's Style property to Bar. Now place the port so that it connects to the D[7..0] pin of the shift register. Press Spacebar to rotate the port as required.

Figure 5. Tying shift register signals to GND.

  • We now need to add bus entries for 'tapping off' individual signals from the output bus of the shift register. These entries need to connect to the individual wires that feed, via respective inverters, into the SLI and SRI inputs of the shift register. From the Wiring toolbar, click the button and place the two bus entries as shown in Figure 6.

Figure 6. Adding bus entries.

  • To tidy up the design and also minimize compilation warnings, we can also place No ERC markers on each of the unused outputs of the Bus Joiner component (U4). From the Wiring toolbar, click the button to enter No ERC marker placement mode. Then position and place a marker on each of the unused pins, O3 to O7, as illustrated in Figure 7.

Figure 7. Mopping up
loose ends with
No ERC markers.

To complete the wiring of our design, we will add labels to key nets in the circuit. This will make the design both easier to understand and also enable any problems to be tracked down with greater efficiency when checking the design at the compilation stage.

  • Go ahead and add net labels to the design, as illustrated in Figure 8, using the Place » Net Label command (or clicking the button on the Wiring toolbar). The net labels shown in Figure 8 are an example. You could use different names for the net labels, as long as they are unique.

Figure 8. Final design - fully wired and net labels attached.

  • Save the schematic and its parent project (File » Save All).

Congratulations! – You have now fully captured the design on the schematic. We can now go on to verify the design and then target and download it to the physical FPGA device.

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