Getting Started Tutorial - Verifying the Design

Frozen Content

Before we look at targeting and downloading our design to the intended physical FPGA device, it is a good time to verify the integrity of the design. To do this, we must invoke Altium Designer's powerful Design Compiler. The process of compiling is integral to producing a valid netlist for a project. The Compiler checks a range of electrical and drafting errors, in accordance with options defined on the Error Reporting and Connection Matrix tabs of the Options for FPGA Project dialog (Project » Project Options).

Figure 1. Compiler settings are defined on the Error Reporting and Connection Matrix tabs of the Options for FPGA Project dialog.

Note: There are no modifications to be made on either of these tabs for the purposes of this tutorial. The default settings are fine.

  • From the main schematic menus, choose Project » Compile FPGA Project Simple_Counter.PrjFpg. Compilation of the project will proceed.
  • Any Warnings, Errors and Fatal Errors will be listed as entries in the Messages panel. If there are any Errors or Fatal Errors found during compilation, this panel will automatically appear. If there are Warnings only, you will need to display the panel manually – simply click on the System button below the main design window and choose Messages from the menu that appears.
    Double-clicking on a message entry will display further information about the error in the Compile Errors panel. The offending entity will be zoomed into and highlighted on the schematic sheet.
  • With the schematic (Simple_Counter.SchDoc) wired correctly, you should only see a number of Warning messages relating to signals having no load (Figure 2). These occur beacause we have tapped off SQ0 and SQ7 from the bus SQ[7..0] but not SQ1 to SQ6. We can safely ignore these warnings for our design.

Figure 2. With the design wired correctly, these are the only messages that should appear after compilation.

If you have any different error messages, you will need to resolve them and recompile the design project.

  • Save the schematic and its parent project.

See Also

Project Compiler Error Reference.

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