EMAC32 - Block Diagram

Figure 1 shows a high-level block diagram for the EMAC32 component.

Figure 1. EMAC32 block diagram.

The internal structure of the Controller consists of a receiver, a transmitter, registers accessible by the Wishbone Slave interface and two distinct dual port RAM blocks – used to implement Transmit and Receive message FIFO buffers respectively. In addition, dedicated registers are used to facilitate read/write access to external memory through a standard Wishbone Master interface.

For information on the internal registers for the EMAC32 that can be accessed from the host processor, see Accessible Internal Registers.