EMAC32 - Accessible Internal Registers

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The following sections detail the internal registers for the EMAC32 Controller, accessible from the host processor.

Receiver Command Register (RX_CMD)

Address: 0h

Access: Read and Write

Value after Reset: 00000000h

This 32-bit register is used to control the Receiver.

Table 1. The RX_CMD register.
MSB                                                                                                                                                                                                                LSB
31
30                                                                                                                                                      7
6
5
4
3
2
1
0
rst
-
crc
ovf
pr
mc
bc
uc
en


Table 2. The RX_CMD register bit functions.
Bit
Symbol
Function

RX_CMD.31

rst

Software Reset bit. Taking this bit High resets the Receiver. This bit must be set and reset by software

RX_CMD.30..RX_CMD.7

-

Not used. Returns 0 when read

RX_CMD.6

crc

Clear CRC Error Counter bit. Setting this bit High will clear the Receiver CRC-Error Counter register (RX_CRC_ERR). This bit must be set and reset by software

RX_CMD.5

ovf

Clear Overflow Flag. This bit must be set and reset by software

RX_CMD.4

pr

Promiscuous Mode bit.

0 = Promiscuous mode disabled
1 = Promiscuous mode enabled. All packets will be received, irrespective of the destination MAC address

RX_CMD.3

mc

Multicast Mode bit.

0 = Multicast mode disabled. No multicast packets will be received
1 = Multicast mode enabled. All multicast packets will be received

RX_CMD.2

bc

Broadcast Mode bit.

0 = Broadcast mode disabled. No broadcast packets will be received
1 = Broadcast mode enabled. All broadcast packets will be received

RX_CMD.1

uc

Unicast Mode bit.

0 = Unicast mode disabled
1 = Unicast mode enabled. All packets will be received whose destination MAC address corresponds to the value held in the Controller's RX_MAC register

RX_CMD.0

en

Receiver Enable bit.

0 = Receiver disabled
1 = Receiver enabled

Receiver Status Register (RX_STATUS)

Address: 1h

Access: Read and Write

Value after Reset: 00000000h

This 32-bit register is used to determine the current state of the Receiver.

Table 3. The RX_STATUS register.
MSB                                                                                                                                                                                                                LSB
31
30                                                          19
18
17
16
15                                                                4
3
2
1
0
rst
-
iovf
ilos
ifo
-
ovf
los
busy
en


Table 4. The RX_STATUS register bit functions.
Bit
Symbol
Function

RX_STATUS.31

rst

Receiver Reset flag. This bit is read-only and is set if the rst bit in the Receiver Command register is set (RX_CMD.31)

RX_STATUS.30..RX_STATUS.19

-

Not used. Returns 0 when read

RX_STATUS.18

iovf

Overflow Interrupt flag. Set if this interrupt is enabled (RX_INT.2 = '1') and an overflow occurs. Writing a '1' to this bit clears the flag.

RX_STATUS.17

ilos

Lack Of Space Interrupt flag. Set if this interrupt is enabled (RX_INT.1 = '1') and a lack-of-space situation occurs. Writing a '1' to this bit clears the flag.

RX_STATUS.16

ifo

Frame OK Interrupt flag. Set if this interrupt is enabled (RX_INT.0 = '1') and the receiver receives a packet. Writing a '1' to this bit clears the flag.

RX_STATUS.15..RX_STATUS.4

-

Not used. Returns 0 when read

RX_STATUS.3

ovf

Overflow flag. This bit is read-only and is set if an overflow occurs

RX_STATUS.2

los

Lack Of Space flag. This bit is read-only and is set if the available space is less than the maximum space needed for a frame

RX_STATUS.1

busy

Busy flag. This bit is read-only and is set if the Receiver is receiving a packet or writing the packet to memory

RX_STATUS.0

en

Receiver Enable flag. This bit is read-only and is set if the Receiver is enabled (i.e. the en bit in the Receiver Command register is set (RX_CMD.0))

Receiver Interrupt Register (RX_INT))

Address: 2h

Access: Read and Write

Value after Reset: 00000000h

This 32-bit register is used to enable/disable the Receiver interrupts.

Table 5. The RX_INT register.
MSB                                                                                                                                                                                                                LSB
31                                                                                                                                                                                         3
2
1
0
-
eovf
elos
efo


Table 6. The RX_INT register bit functions.
Bit
Symbol
Function

RX_INT.31..RX_INT.3

-

Not used. Returns 0 when read

RX_INT.2

eovf

Receiver Overflow Interrupt Enable. Set this bit High to enable generation of an interrupt when an overflow occurs

RX_INT.1

elos

Receiver Lack-Of-Space Interrupt Enable. Set this bit High to enable generation of an interrupt when the available space in the Receive Buffer is less than that required for a frame

RX_INT.0

efo

Receiver Frame-OK Interrupt Enable. Set this bit High to enable generation of an interrupt when the Receiver receives a packet of data

Receiver CRC-Error Counter Register (RX_CRC_ERR)

Address: 3h

Access: Read-only

Value after Reset: 00000000h

This 32-bit register is used to count the number of packets received which have a CRC error, since the last time the register was cleared. This register can be cleared (reset to 0) by setting the crc bit in the Receiver Command register (RX_CMD.6).

Receiver Start Address Register (RX_START)

Address: 4h

Access: Read and Write

Value after Reset: 00000000h

This 32-bit register is used to define the start address for the Receive Buffer in external memory, which is accessed through the Controller's Wishbone Master interface.

The full start address is composed of a 12-bit Base address (bits 31..20) and an 18-bit Start address (bits 19..2).

The width of the memory used for the Receive Buffer is actually 32 bits. The address must be located at a 32-bit boundary and therefore the value stored for the start address must be a multiple of 4. Bits 1..0 are therefore always '0'.

Table 7. The RX_START register.
MSB                                                                                                                                                                                                                LSB
31                                                                                     20 19                                                                                                           2
1
0
base_address
start_address
0
0


Table 8. The RX_START register bit functions.
Bit
Symbol
Function

RX_START.31..RX_START.20

base_address

Value of these bits is used in all Receive Buffer related registers as bits 31..20 of the address.

RX_START.19..RX_START.2

start_address

Second part of the Receive Buffer start address.

RX_START.1..RX_START.0

0

Always returns 0 when read

Receiver End Address Register (RX_END)

Address: 5h

Access: Read and Write

Value after Reset: 00000000h

This 32-bit register is used to define the end address for the Receive Buffer in external memory, which is accessed through the Controller's Wishbone Master interface. It is used to calculate the available memory in the buffer.

The full end address is the concatenation of RX_START[31..20] and RX_END[19..2].

The width of the memory used for the Receive Buffer is actually 32 bits. The address must be located at a 32-bit boundary and therefore the value stored for the end address must be a multiple of 4. Bits 1..0 are therefore always '0'.

Table 9. The RX_END register.
MSB                                                                                                                                                                                                                LSB
31                                                                                     20 19                                                                                                           2
1
0
base_address
end_address
0
0


Table 10. The RX_END register bit functions.
Bit
Symbol
Function

RX_END.31..RX_END.20

base_address

These 12 bits are read-only and are a copy of RX_START[31..20]

RX_END.19..RX_END.2

end_address

Second part of the Receive Buffer end address.

RX_END.1..RX_END.0

0

Always returns 0 when read

Receiver Input Address Register (RX_INPUT)

Address: 6h

Access: Read and Write

Value after Reset: 00000000h

This 32-bit register is used to set the input address for the Receive Buffer in external memory, which is accessed through the Controller's Wishbone Master interface. It points to the memory location where the next packet will be written.

The full input address is the concatenation of RX_START[31..20] and RX_INPUT[19..2].

The RX_INPUT register is used, in conjunction with the RX_OUTPUT register, for control purposes – such as determining when the Receive Buffer is empty or full, when wrapping in memory is required, etc. For further information, see Receive Buffer Usage.

This register is updated automatically by the Controller. Therefore, you only need to write to this register once, at initialization, setting input_address to be the same value as start_address in the RX_START register.

If the available space between the input address and the end address is less than the maximum space needed for a packet, the contents of the memory at the input address is set to 00000000h and the input address is set to the start address of the Receive Buffer.

If the available space between the input address and the output address is less than the maximum space needed for a packet (i.e. output address is higher than the input address) a lack-of-space situation occurs.

The width of the memory used for the Receive Buffer is actually 32 bits. The address must be located at a 32-bit boundary and therefore the value stored for the input address must be a multiple of 4. Bits 1..0 are therefore always '0'.

Table 11. The RX_INPUT register.
MSB                                                                                                                                                                                                                LSB
31                                                                                     20 19                                                                                                           2
1
0
base_address
input_address
0
0


Table 12. The RX_INPUT register bit functions.
Bit
Symbol
Function

RX_INPUT.31..RX_INPUT.20

base_address

These 12 bits are read-only and are a copy of RX_START[31..20]

RX_INPUT.19..RX_INPUT.2

input_address

Second part of the Receive Buffer input address.

RX_INPUT.1..RX_INPUT.0

0

Always returns 0 when read

Receiver Output Address Register (RX_OUTPUT)

Address: 7h

Access: Read and Write

Value after Reset: 00000000h

This 32-bit register is used to set the output address for the Receive Buffer in external memory, which is accessed through the Controller's Wishbone Master interface. It points to the memory location up to which packets will be read by software.

The full output address is the concatenation of RX_START[31..20] and RX_OUTPUT[19..2].

The RX_OUTPUT register is used, in conjunction with the RX_INPUT register, for control purposes – such as determining when the Receive Buffer is empty or full, when wrapping in memory is required, etc. For further information, see Receive Buffer Usage.

The RX_OUTPUT register must be written by software.

If the contents of the memory at the output address is set to 00000000h, the next packet must be read at the start address of the Receive Buffer. If the output address equals the input address, the Receive Buffer is empty.

The width of the memory used for the Receive Buffer is actually 32 bits. The address must be located at a 32-bit boundary and therefore the value stored for the output address must be a multiple of 4. Bits 1..0 are therefore always '0'.

Table 13. The RX_OUTPUT register.
MSB                                                                                                                                                                                                                LSB
31                                                                                     20 19                                                                                                           2
1
0
base_address
output_address
0
0


Table 14. The RX_OUTPUT register bit functions.
Bit
Symbol
Function

RX_OUTPUT.31..RX_OUTPUT.20

base_address

These 12 bits are read-only and are a copy of RX_START[31..20]

RX_OUTPUT.19..RX_OUTPUT.2

output_address

Second part of the Receive Buffer output address

RX_OUTPUT.1..RX_OUTPUT.0

0

Always returns 0 when read

Receiver MAC Address Register (RX_MAC1, RX_MAC2)

Address: 8h and 9h

Access: Read and Write

Value after Reset: 00000000h

These 32-bit registers are used to define the 48-bit MAC address of the Receiver. The MAC address is only used by the Receiver when Unicast mode is enabled (uc bit set in the Receiver Command register (RX_CMD.1)).

The address is used by the Receiver to determine if a message on the bus is addressed to it or not (contained within the Destination Address field of the message frame).

This address is not used for transmission. Instead, a separate (and quite possibly different) MAC address must be entered into the Source Address field of a frame to be transmitted.

Table 15. The RX_MAC1 register.
MSB                                                                                                                                                                                                                LSB
31                                             24 23                                             16 15                                             8 7                                             0
mac_addr 7..0
mac_addr 15..8
mac_addr 23..16
mac_addr 31..24


Table 16. The RX_MAC2 register.
MSB                                                                                                                                                                                                                LSB
31                                                                                                        16 15                                             8 7                                             0
-
mac_addr 39..32
mac_addr 47..40


Bits 31..16 of the RX_MAC2 register are not used and will return 0 when read.

Transmitter Command Register (TX_CMD)

Address: 10h

Access: Read and Write

Value after Reset: 00000000h

This 32-bit register is used to control the Transmitter.

Table 17. The TX_CMD register.
MSB                                                                                                                                                                                                                LSB
31
30                                                                                                                                                                                         2
1
0
rst
-
fd
enable


Table 18. The TX_CMD register bit functions.
Bit
Symbol
Function

TX_CMD.31

rst

Software Reset bit. Taking this bit High resets the Transmitter. This bit must be set and reset by software

TX_CMD.30..TX_CMD.2

-

Not used. Returns 0 when read

TX_CMD.1

fd

This bit controls the full-duplex/half-duplex mode.

0 = Half Duplex
1 = Full Duplex

TX_CMD.0

enable

Transmitter Enable bit.

0 = Transmitter disabled
1 = Transmitter enabled

Transmitter Status Register (TX_STATUS)

Address: 11h

Access: Read and Write

Value after Reset: 00000000h

This 32-bit register is used to determine the current state of the Transmitter.

Table 19. The TX_STATUS register.
MSB                                                                                                                                                                                                                LSB
31
30                                                  20
19
18
17
16
15                                              5
4
3
2
1
0
rst
-
ilen
icol
iemp
ifs
-
len
col
emp
busy
en


Table 20. The TX_STATUS register bit functions.
Bit
Symbol
Function

TX_STATUS.31

rst

Transmitter Reset flag. This bit is read-only and is set if the rst bit in the Transmitter Command register is set (TX_CMD.31)

TX_STATUS.30..TX_STATUS.20

-

Not used. Returns 0 when read

TX_STATUS.19

ilen

Length Error Interrupt flag. Set if this interrupt is enabled (TX_INT.3 = 1) and a length error occurs. Writing a '1' to this bit clears the flag.

TX_STATUS.18

icol

Collision Error Interrupt flag. Set if this interrupt is enabled (TX_INT.2 = 1) and more than 15 collisions have occurred. Writing a '1' to this bit clears the flag.

TX_STATUS.17

iemp

Transmitter Empty Interrupt flag. Set if this interrupt is enabled (TX_INT.1 = 1) and the Transmit Buffer becomes empty. Writing a '1' to this bit clears the flag.

TX_STATUS.16

ifs

Frame Sent Interrupt flag. Set if this interrupt is enabled (TX_INT.0 = 1) and the Transmitter has sent a packet. Writing a '1' to this bit clears the flag.

TX_STATUS.15..TX_STATUS.5

-

Not used. Returns 0 when read

TX_STATUS.4

len

Length Error flag. This bit is read-only and is set if the length read from the Transmit Buffer is invalid (exceeds the maximum length of a packet)

TX_STATUS.3

col

Collision Error flag. This bit is read-only and is set if more than 15 collisions occur.

TX_STATUS.2

emp

Transmit Buffer Empty flag. This bit is read-only and is set if the Transmit Buffer is empty

TX_STATUS.1

busy

Busy flag. This bit is read-only and is set if the Transmitter is sending a packet.

TX_STATUS.0

en

Transmitter Enable flag. This bit is read-only and is set if the Transmitter is enabled (i.e. the en bit in the Transmitter Command register is set (TX_CMD.0)

Transmitter Interrupt Register (TX_INT)

Address: 12h

Access: Read and Write

Value after Reset: 00000000h

This 32-bit register is used to enable/disable the Transmitter interrupts.

Table 21. The TX_INT register.
MSB                                                                                                                                                                                                                LSB
31                                                                                                                                                                          4
3
2
1
0
-
elen
ecol
eemp
efs


Table 22. The TX_INT register bit functions.
Bit
Symbol
Function

TX_INT.31..TX_INT.4

-

Not used. Returns 0 when read

TX_INT.3

elen

Transmitter Length Error Interrupt Enable. Set this bit High to enable generation of an interrupt when a length error occurs

TX_INT.2

ecol

Transmitter Collision Error Interrupt Enable. Set this bit High to enable generation of an interrupt if more than 15 collisions occur.

TX_INT.1

eemp

Transmitter Empty Interrupt Enable. Set this bit High to enable generation of an interrupt if the Transmit Buffer becomes empty

TX_INT.0

efs

Transmitter Frame-Sent Interrupt Enable. Set this bit High to enable generation of an interrupt when the Transmitter sends a packet of data

Transmitter Collision-Error Counter Register (TX_COL_ERR)

Address: 13h

Access: Read-only

Value after Reset: 0h

The lower 4 bits of this 32-bit register are used to count the number of collisions. The counter is cleared after a successful transmission. If the counter counts past 15, the Transmitter is disabled. Enabling the Transmitter again resets the collision counter.

Bits 31..5 of this register are not used and will return 0 when read.

Transmitter Start Address Register (TX_START)

Address: 14h

Access: Read and Write

Value after Reset: 00000000h

This 32-bit register is used to define the start address for the Transmit Buffer in external memory, which is accessed through the Controller's Wishbone Master interface.

The full start address is composed of a 12-bit Base address (bits 31..20) and an 18-bit Start address (bits 19..2).

The width of the memory used for the Transmit Buffer is actually 32 bits. The address must be located at a 32-bit boundary and therefore the value stored for the start address must be a multiple of 4. Bits 1..0 are therefore always '0'.

Table 23. The TX_START register.
MSB                                                                                                                                                                                                                LSB
31                                                                                     20 19                                                                                                           2
1
0
base_address
start_address
0
0


Table 24. The TX_START register bit functions.
Bit
Symbol
Function

TX_START.31..TX_START.20

base_address

Value of these bits is used in all Transmit Buffer related registers as bits 31..20 of the address.

TX_START.19..TX_START.2

start_address

Second part of the Transmit Buffer start address.

TX_START.1..TX_START.0

0

Always returns 0 when read

Transmitter End Address Register (TX_END)

Address: 15h

Access: Read and Write

Value after Reset: 00000000h

This 32-bit register is used to define the end address for the Transmit Buffer in external memory, accessed through the Controller's Wishbone Master interface.

The full end address is the concatenation of TX_START[31..20] and TX_END[19..2].

The width of the memory used for the Transmit Buffer is actually 32 bits. The address must be located at a 32-bit boundary and therefore the value stored for the end address must be a multiple of 4. Bits 1..0 are therefore always '0'.

Table 25. The TX_END register.
MSB                                                                                                                                                                                                                LSB
31                                                                                     20 19                                                                                                           2
1
0
base_address
end_address
0
0


Table 26. The TX_END register bit functions.
Bit
Symbol
Function

TX_END.31..TX_END.20

base_address

These 12 bits are read-only and are a copy of TX_START[31..20]

TX_END.19..TX_END.2

end_address

Second part of the Transmit Buffer end address.

TX_END.1..TX_END.0

0

Always returns 0 when read

Transmitter Input Address Register (TX_INPUT)

Address: 16h

Access: Read and Write

Value after Reset: 00000000h

This 32-bit register is used to set the input address for the Transmit Buffer in external memory, which is accessed through the Controller's Wishbone Master interface. It points to the memory location where the next packet will be written by software. This register must be updated by software.

The full input address is the concatenation of TX_START[31..20] and TX_INPUT[19..2].

The TX_INPUT register is used, in conjunction with the TX_OUTPUT register, for control purposes – such as determining when the Transmit Buffer is empty or full, when wrapping in memory is required, etc. For further information, see Transmit Buffer Usage.

If the available space between the input address and the end address is less than the space needed for the next packet, the contents of the memory at the input address must be set to 00000000h and the input address must be set to the start address of the Transmit Buffer.

The width of the memory used for the Transmit Buffer is actually 32 bits. The address must be located at a 32-bit boundary and therefore the value stored for the input address must be a multiple of 4. Bits 1..0 are therefore always '0'.

Table 27. The TX_INPUT register.
MSB                                                                                                                                                                                                                LSB
31                                                                                     20 19                                                                                                           2
1
0
base_address
input_address
0
0


Table 28. The TX_INPUT register bit functions.
Bit
Symbol
Function

TX_INPUT.31..TX_INPUT.20

base_address

These 12 bits are read-only and are a copy of TX_START[31..20]

TX_INPUT.19..TX_INPUT.2

input_address

Second part of the Transmit Buffer input address.

TX_INPUT.1..TX_INPUT.0

0

Always returns 0 when read

Transmitter Output Address Register (TX_OUTPUT)

Address: 17h

Access: Read and Write

Value after Reset: 00000000h

This 32-bit register is used to set the output address for the Transmit Buffer in external memory, which is accessed through the Controller's Wishbone Master interface. It points to the memory location up to which packets will be read (and sent) by the Controller.

The full output address is the concatenation of TX_START[31..20] and TX_OUTPUT[19..2].

The TX_OUTPUT register is used, in conjunction with the TX_INPUT register, for control purposes – such as determining when the Transmit Buffer is empty or full, when wrapping in memory is required, etc. For further information, see Transmit Buffer Usage.

The TX_OUTPUT register is updated by the Controller. Therefore, you only need to write to this register once, at initialization, setting output_address to be the same value as start_address in the TX_START register.

If the output address is 00000000h, the next packet will be read at the start address of the Transmit Buffer. If the output address equals the input address, the Transmit Buffer is empty.

The width of the memory used for the Transmit Buffer is actually 32 bits. The address must be located at a 32-bit boundary and therefore the value stored for the output address must be a multiple of 4. Bits 1..0 are therefore always '0'

Table 29. The TX_OUTPUT register.
MSB                                                                                                                                                                                                                LSB
31                                                                                     20 19                                                                                                           2
1
0
base_address
output_address
0
0


Table 30. The TX_OUTPUT register bit functions.
Bit
Symbol
Function

TX_OUTPUT.31..TX_OUTPUT.20

base_address

These 12 bits are read-only and are a copy of TX_START[31..20]

TX_OUTPUT.19..TX_OUTPUT.2

output_address

Second part of the Transmit Buffer output address

TX_OUTPUT.1..TX_OUTPUT.0

0

Always returns 0 when read

PHY Command Register (PHY_CMD)

Address: 1Ch

Access: Read and Write

Value after Reset: 00000000h

This 32-bit register is used to control the writing to/reading from internal registers of the connected PHY Controller device.
 

This register should only be written to if no other action is pending.


Table 31. The PHY_CMD register.

MSB                                                                                                                                                                                                                LSB
31
30                                                                                                                                                                                               2
1
0
rst
-
rrd
rwr


Table 32. PHY_CMD register bit functions.
Bit
Symbol
Function

PHY_CMD.31

rst

Reset bit. Set High to reset the PHY interface.

PHY_CMD.30..PHY_CMD.2

-

Not used. Returns 0 when read

PHY_CMD.1

rrd

Register Read bit. Set High to read from the addressed internal PHY register

PHY_CMD.0

rwr

Register Write bit. Set High to write to the addressed internal PHY register

PHY Address Register (PHY_ADDR)

Address: 1Dh

Access: Read and Write

Value after Reset: 00000001h

This 32-bit register is used to load the address of the PHY Controller device connected to the EMAC32 Controller. The PHY address is five bits in length. Bits 31..5 of this register are therefore unused and will return 0 when read.
 

This register should only be written to if no other action is pending.

PHY Internal Register Address Register (REG_ADDR)

Address: 1Eh

Access: Read and Write

Value after Reset: 00000000h

This 32-bit register is used to load the unique address of an internal register of the connected PHY device that you wish to write to/read from. The internal register address is five bits in length. Bits 31..5 of this register are therefore unused and will return 0 when read.
 

This register should only be written to if no other action is pending.

PHY Data Output Register (PHY_DAT)

Address: 1Fh

Access: Read and Write

Value after Reset: 00000000h

This 32-bit register is used to store the data to be written to the accessed internal register of the connected PHY Controller device in the case of a write operation, and to store the data received from that register in the case of a read operation. The data is 16 bits in length. Bits 31..16 of this register are not used and will return 0 when read.
 

The content of the PHY_DAT register gets corrupted when performing a write operation. This register should only be written to if no other action is pending.

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