BT656 - Host to Controller Communications
Communications between a 32-bit host processor and the BT656 Controller are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible internal registers, see Wishbone Communications - 32-bit Processor to Slave Peripheral.
Table 1 summarizes how the 32-bit data word from the host processor is used by each of the internal registers.
Table 1. Values loaded into internal registers during a write.| Internal Register | Value loaded into register |
|---|---|
| MODE | WBS_DAT_I(4..0) |
| START | WBS_DAT_I(31..2) |
| SIZE | WBS_DAT_I(20..2) |
| BPL | WBS_DAT_I(12..0) |
| VBPL | WBS_DAT_I(11..0) |
| SCALE | WBS_DAT_I(11..0) |
Table 2 summarizes the 'make-up' of the 32-bit data word that is read back from each register.
Table 2. Values read from internal registers during a read.| Internal Register | Value presented to host processor |
|---|---|
| MODE | "000000000000000000000000000" & MODE(4..0) |
| STATUS | "000000000000000000000000000" & STATUS(4..0) |
| START | START(29..0) & "00" |
| SIZE | "00000000000" & SIZE(18..0) & "00" |
| BPL | "00000000000000000000" & BPL(11..0) |
| VBPL | "00000000000000000000" & VBPL(11..0) |
| SCALE | "00000000000000000000" & SCALE(11..0) |