Breakpoints

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Function

The Breakpoints panel provides information on all breakpoints that are currently defined in all open VHDL source files (irrespective of the parent FPGA project (*.PrjFpg) they belong to), as well as providing commands for enabling, disabling and deleting selected breakpoints as required.

Content and Use

Any breakpoints that are currently defined in any open VHDL source documents (*.VHD, *.VHDTST) will be listed in the panel. For each breakpoint entry, the following information is available:

  • Filename - the name of the source document in which the breakpoint resides
  • Line Number - the line number within the source document at which the breakpoint has been placed.

A small icon to the left of the Filename is used to indicate the status of the breakpoint:

-

Breakpoint is valid and currently enabled

-

Breakpoint is valid and currently disabled

-

Invalid breakpoint

The icons used to represent breakpoints are also used when marking breakpoints on the source code document itself. The line of code to which a breakpoint applies is also highlighted using the associated breakpoint status color, as illustrated in the following image.

Double-clicking on a breakpoint entry in the panel will place the text cursor within the line of code to which the breakpoint applies. If the line of code is not currently within the visible area of the design editor window, it will be made so.

Note: If the associated source VHDL document is not currently the active document in the design editor window, it will not be made so automatically.

Right-click Menu

The right-click pop-up menu for the panel provides the following commands:

  • Enable - toggle the state of the selected breakpoint between enabled and disabled
  • Delete - delete the selected breakpoint
  • Enable All - change the current state of all breakpoints listed in the panel to enabled
  • Disable All - change the current state of all breakpoints listed in the panel to disabled
  • Delete All - delete all currently defined breakpoints listed in the panel.

Notes

  • A breakpoint tells the VHDL Simulation Debugger to pause its execution of program code at a particular line in a source document. Include a breakpoint when you wish to halt execution at a specific point. A typical use of breakpoints in a source code document would be in the different branches of a conditional statement, where a breakpoint is inserted into each branch to check which one is executed.
  • When a VHDL simulation session is started, all lines of code that can be executed are distinguished by the use of a 'dot' in the right-hand margin, as illustrated below:

As breakpoints can only be valid when placed on executable lines of code, these visual indicators should be used to effectively (and correctly) define such breakpoints.

  • Breakpoints can only be added directly from within a source document, by clicking in the right-hand margin next to the line that you wish to apply a breakpoint to. Clicking again will remove the breakpoint. A newly added breakpoint (valid or invalid) will be enabled by default.
  • A disabled breakpoint remains defined but will not cause the debugger to pause code execution when encountered.
  • An invalid breakpoint, irrespective of whether it is enabled, will be ignored by the debugger during code execution.
  • There are three cases when a breakpoint is deemed invalid:
    1. It is validly defined but a VHDL simulation session for its parent FPGA project is not currently running
    2. A VHDL simulation session is running, but it has been placed on a line of source code that is non-executable
    3. A VHDL simulation session is running, but it resides in a source code document that is not part of the source for the FPGA project currently being debugged.
  • The keyboard shortcuts Up Arrow (or Left Arrow), HOME, END and Down Arrow (or Right Arrow), can be used to select the previous, first, last and next breakpoint entry, respectively.
  • To continue execution of code that has been halted at a breakpoint, use the Run Forever command, available from the Simulator menu or VHDL Tools toolbar [shortcut: F9], or use the various single stepping/additional run commands available.

See Also

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