Sharing Multiple Slave Devices Between Processors
Some FPGA designs may require shared processor access to more than one slave memory or peripheral I/O device. In the OpenBus System, this is catered for by using both an Interconnect component and an Arbiter component, with the Arbiter placed before the Interconnect.
These devices facilitate connection of two (or more) processor masters to a whole bank of slave devices. The devices would be mapped into the respective processor address spaces at identical locations. The following figures show examples of using Interconnect and Arbiter components to allow two TSK3000A processors to access a variety of physical slave memory (Figure 1) and peripheral I/O (Figure 2) devices.
Figure 1. Sharing multiple slave memory devices between two processors.
Figure 2. Sharing multiple slave peripheral I/O devices between two processors.