A Word on Connecting External Memory...

When connecting to physical memory outside of the FPGA device, the wiring involved will depend on the type of memory and where it is located.

If the memory is located on a NanoBoard or a plug-in daughter board, simply place the appropriately-configured Memory Controller within the OpenBus System, connected to the processor's MEM port through an Interconnect component. On the top-level schematic, the external memory interface signals are wired from the sheet symbol (used to reference the underlying OpenBus System document) to the relevant port component(s). This situation is shown in Figure 1 for physical memory located on a daughter board plugged into a Desktop NanoBoard NB2DSK01.

Figure 1. Interfacing to external memory on a plug-in duaghter board.

Note: Port components can be found in the available port-plugin integrated libraries, located in the \Library\Fpga folder of the installation. The particular library used will depend on the type of NanoBoard you are using. For a NanoBoard-NB1, the relevant components can be found in FPGA NB1 Port-Plugin.IntLib. For a Desktop NanoBoard NB2DSK01, the relevant components can be found in FPGA DB Common Port-Plugin.IntLib.

If the memory device resides elsewhere – for example on a production board or a third party development board – and the memory device is of a type supported by Altium Designer's Wishbone Memory Controller (SRAM, SDRAM, BRAM, Flash) – then instead of a port component, you will need to place and wire up ports corresponding to the I/O lines to/from the memory device. Figure 2 shows an example of this.

Figure 2. Interfacing to external memory non-resident on Altium hardware.

If the memory device is not of a type supported by the Wishbone Memory Controller, you would need to write your own VHDL to effectively provide interface control between the Interconnect component and the external memory device.

A sheet symbol referencing the entity in your VHDL code would be included on the top-level schematic of the FPGA design. You would need to expose the relevant signals from the Interconnect component – external to the OpenBus System document. This is achieved by connecting from the Interconnect component to a Bus Exporter component. Figure 3 illustrates an example, whereby the custom memory controller is defined within a referenced sub-file, Mem_Ctrl.vhd.

Figure 3. Interfacing to external memory using a custom memory controller.