Configuring the Constraints

Configurations provide a way for an Altium Designer project to be managed parametrically. For embedded projects this could allow a separate set of settings to be maintained for a debug version and a release version of the product. For a PCB project configurations create the scope for rules to be specified in a separate file, allowing different versions of the board to be developed with different rules.

Focusing specifically on FPGA projects, configurations allow the design to be developed without the need to specify either tool settings or target-device settings, such as project port to device pin mappings, on the source documents.

There are a number of classes of configuration information within an FPGA project.

Specific to the Device and Board

This is where pin information is considered. The physical location of a pin on a device is specific to the combination of a given device and a given board.

Each logical port at the top level of an FPGA design is given a logical name which can be used to reference the pin in a device-independent way. This logical port must be mapped to a physical pin on the target device. The final location of this pin on the device will be driven by board-level issues, such as how the pin best connects to other resources on the board.

For example a data pin, say DATA3, for a particular board may be implemented as pin 21 on a Xilinx QFP package, and as pin H7 on an Altera BGA package. So the same port may be connected through a different pin on a different device, or even if the device is the same, the port may be connected through a different pin on a different board layout. From the logical design perspective, there would be multiple configurations, one for each of these scenarios. Each would have a pin description that included the logical name DATA3, but the physical pin being described would be different.

Another example of device/board specific requirements is pin configuration constraints. For example, if the FPGA device is connected to a 2.5 volt device on one board and a 3.3 volt device on another, then the setup data for the pin can be defined as a constraint for that device and target board.

These constraints could be defined as a description of how a specific device is connected to the resources on a specific PCB.

Specific to a Certain Device

This would include specifications for how to use internal features of the particular device. A good example would be place and route controls for FPGA tools – these are very device specific, but do not have any impact on the way the device is connected to the outside world.

These constraints could be defined as a description of how to configure a specific device's internal resources for a specific FPGA design.

Specific to a Project or Design

This would include requirements which are associated with the logic of the design, as well as constraints on its timing. For example, specifying that a particular logical port must be allocated to a global clock net, and must be able to run at a certain speed. This class of constraint could be added directly to the source documents of the FPGA design. Defining them as separate from the source documents allows the design itself to be more parametric.

These constraints could be defined as a description of how to configure a specific FPGA design.