XC3S1500-4FG676C - Feature Summary
The XC3S1500-4FG676C device is a member of the 1.2V Spartan-3 family of FPGAs. The Spartan-3 provides a low-cost, high-density solution for applications such as those targeted to the consumer electronics industry.
The entire Spartan-3 family includes eight devices offering densities ranging from 50,000 to 5,000,000 gates. The XC3S1500-4FG676C offers 1.5 million gates. Table 1 provides an information summary for this device.
In order to use the Spartan-3 device, you will need to install the relevant Vendor tools – Xilinx® ISE™ or Xilinx ISE WebPACK® from www.xilinx.com.
Feature | Description |
---|---|
Device Name | XC3S1500-4FG676C |
Vendor | Xilinx |
Family | Spartan-3 |
Package | 676-Ball Fine Pitch Ball Grid Array (FG676) |
Speed Grade | Standard |
Temperature Grade | Commercial |
Pin Count | 676 |
Maximum User I/O Pins | 487 |
Max. Differential I/O Pairs | 221 |
System Gates | 1,500,000 |
Xilinx Logic Cells | 29,952 |
CLB Array | 3,328 CLBs (64 rows by 52 columns). (1 CLB = 4 Slices, giving 13,312 Slices). |
Embedded (Block) RAM | 576K bits |
Distributed RAM | 208K bits |
Embedded Multipliers (18x18) | 32 |
Digital Clock Managers (DCM) | 4 |
Global Clock Resources | 8 |
Configuration Memory Required | 5,214,784 bits |
On-Chip Termination Support | Yes |
Location on Board
The Spartan-3 device (designated U1
) is located on the component side and in the lower half of the board.
Schematic Reference
The Spartan-3 device and related circuitry can be found on the following sheets of the daughter board schematics:
DEVICES.SchDoc
(entitled FPGA, LEDs and SRAM Memory)
FPGA.SchDoc
(entitled FPGA Connections)
FPGA_NonIO.SchDoc
(entitled FPGA Power and Programming)
Bypass_FPGA_1V2.SchDoc
(entitled FPGA Bypass 1V2)
Bypass_FPGA_2V5.SchDoc
(entitled FPGA Bypass 2V5)
Bypass_FPGA_3V3.SchDoc
(entitled FPGA Bypass 3V3).
Further Device Information
For more information on the XC3S1500-4FG676C device, refer to the datasheet (dso99.pdf
) available at www.xilinx.com.