The Hard Devices Chain
The Hard Devices chain (Figure 1) shows all target programmable devices detected by the system. This includes FPGAs resident on daughter board plug-ins, as well as all JTAG devices found on any user boards connected to a NanoBoard in the configuration. Any discrete processors will also be presented in this chain.
The NanoTalk Controller automatically detects and configures appropriate devices so that they form a continuous chain using their physical TDI and TDO JTAG lines. If a physical device (typically on a user board) is not supported by the system, it will appear in the chain as a Generic JTAG device. To ensure continuity of the Hard JTAG chain, a corresponding Boundary Scan Description Language(BSDL) file must be attached to the device, the contents of which are used by the system to correctly configure the JTAG chain.
Each physical device in the chain that is programmable from Altium Designer will have a Process Flow associated to it. The stages in this flow are used to interactively compile, synthesize, build and ultimately program the device, all from within the Devices view.
Figure 1. The Hard Devices chain.