SDRAM Interface Clocking for the NanoBoard 2
NB2 + DB30 Xilinx Spartan 3 DaughterBoard
1. Schematic wiring for Xilinx DCM clocks.
2. Shared Memory Port Plugin wiring.
NB2 + DB31 Altera Cyclone II DaughterBoard
1. Alteral PLL wiring.
2. Shared Memory Port PlugIn wiring.
Step by step Clock manager generation:
DB30 DaughterBoard
Wishbone Clock and Sdram Memory controller clock generation
1. Start CoreGenerator from ISE Accessories menu.
2. Go to FILE->NEW PROJECT and browse to your project location. Type in project name "MainClock" and save your project.
3. In the project options dialog select family, device, package and speed grade.
Figure 1. Launching the Xilinx Core Generator to generate the SDRAM Clock Manager.
Click OK button.
4. Browse to "FPGA Features and Design/Clocking/Spartan-3E, Spartan-3A/Single DCM_SP" component and double click it.
Figure 2. Select the DCM (Digital Clock Manager) option.
5. Provide Component name: MainClock and hit OK button.
Figure 3. Specify the name for the new DCM.
6. Select Output file type and XST as Synthesis Tool.
Figure 4. Select the output file type and synthesis tool.
7. General Setup page.
Provide input clock frequency and enable CLK2X output port.
CLK0 output becomes our Wishbone Clock and CLK2X is a copy of it with frequency multiplied by 2. This is our Memory Controller clock that we use internally in FPGA.
LOCKED output will give us indication when the DCM is 'locked' to input clock indicating that all outputs are stable.
"CLKIN Source" and "Feedback Source" group boxes allow us to enable IOB buffer insertion as well as internal feedback clock buffering via BUFG. This is Xilinx specific and is automatically done by Altium Designer when you build your design.
We can set both to 'internal'.
Click Next.
8. Select Use Global Buffers for all selected clock outputs option.
This will insert Xilinx clock buffers in the output forcing place and route tool to place our clocks on dedicated global clock lines.
Figure 6. Enable Global Buffers for all output clocks.
Click Next.
9. Review all options and click on Finish button.
This will produce our MainClock.vhd file which we can add to our design.
Figure 7. Review configuration and generate output files.
Sdram Clock Board Deskew DCM
1. Go FILE->NEW PROJECT and browse to your project location. Type in project name "SdramBoardDeskew" and save your project.
2. in the project options dialog select family, device, package and speed grade.
Figure 8. Configure the Core Generator for Spartan 3AN target.
4. Browse to "FPGA Features and Design/Clocking/Spartan-3E, Spartan-3A/Single DCM_SP" component and double click it.
Figure 9.Select the DCM (Digital Clock Manager) option.
5. Provide Component name: SdramBoardDeskew and hit OK button.
Figure 10. Specify the name for the new DCM.
6. Select Output file type and XST as Synthesis Tool.
Figure 11. Select the output file type and synthesis tool.
7. General Setup page.
Provide input clock frequency 80MHz. This pins is driven by 80MHz clock generated in MainClock DCM.
CLKIN Source is internal as this input clock is already buffered in MainClock DCM.
Feedback Source is external for this DCM. This will be wired to BUS_SDRAM_FEEDBACK pin.
Figure 12. Configure Digital Clock Manager.
8. Select Use Global Buffers for all selected clock outputs option.
This will insert Xilinx clock buffers in the output forcing place and route tool to place our clocks on dedicated global clock lines.
Figure 13. Enable Global Buffers for all output clocks.
9.Review all options and click on Finish button.
This will produce our SdramBoardDeskew.vhd file which we can add to our design.
Figure 14. Review configuration and generate output files.
DB31 DaughterBoard
1. Launch the Altera MegaWizard Plug-In Manager.
2. Create a new custom megafunction variation.
Figure 15. Launching the Altera Megafunction Wizard.
Click Next
2. Configure the MegaWizard Plug-In Manger for Cyclone III target.
Browse to your project location and type in the output file name "SdramClocking"
Select ALTPLL megafunction from the list.
Figure 16. Specifying the Megafunction Options.
Click Next
3. Specify input clock frequency.
Figure 17. Setting the target clock frequency.
Click Next
4. Enable 'areset' input port and 'locked' output port.
Figure 18. Enabling optional pins.
Click Next
5.Turn off second input clock generation.
Figure 19. Turning off second input clock port.
6. Configure Wishbone Clock port.
Set output frequency to 40MHz. This is our system Wishbone Clock.
Figure 20. Specify the Wishbone Clock frequency.
Click Next
7. Configure Memory Controller clock.
Specify Memory Controller Clock frequency.
Figure 21. Configuring the Memory Controller Sdram Clock.
Click Next
8. Configure Sdram Memory Clock
Select 'Use this clock' option and specify input frequency 40 MHz.
Figure 22. Specifying the Sdram Memory clock.
Click Next
9. Discard simulation library option.
Figure 23. Click Next
Click Next
10. Generate output files.
Figure 24. Generating output files.
11. Click on Finish button and the MegaWizard Plug-in Manager will generate output files.