NanoBoard 3000 - Audio CODEC

Parent article: NanoBoard 3000 - Motherboard Resources

As part of its high-quality audio sub-system, the NanoBoard 3000 provides a CS4270 24-bit, 192kHz stereo audio CODEC (from Cirrus Logic). The CODEC caters for both analog and digital audio I/O.

CS4270 Stereo Audio CODEC device.

Device Power and Reset

Power for the digital section of the device, as well as the signal level for the device's Control Port, is sourced direct from the motherboard's 3.3V supply.

The analog sections of the device are powered from a regulated 3.3V power supply, obtained by passing the motherboard's 5V supply through a low dropout (LDO) regulator (a TC1017R, from Microchip).

Reset of the CS4270 is performed by taking its RST input Low. The reset signal to this input is sourced from the output of a supervisory reset circuit device – a MAX6315, from Maxim. This device will assert the reset signal to the CS4270 if its 3.3V supply voltage dips below 2.63V (nominal), thereby providing power-up reset of the CODEC. The reset signal will remain asserted for a minimum of 1ms (typically 1.5ms) after the supply voltage rises above this threshold.

Analog Audio I/O

Analog audio input to the CS4270 consists of a pair of stereo line inputs (LineIn_L, LineIn_R). These signals, derived from the motherboard's 'LINE IN' input, are fed into the device's AINA and AINB pins respectively.

Analog audio output is in the form of two signals – LineOut_L and LineOut_R. These signals are sourced from the CS4270's AOUTA and AOUTB pins. Both outputs are passed through low-pass filters – simple RC filtering providing a cut-off frequency of around 37kHz. The signals are then subsequently routed to the analog mixer on the motherboard. From here they are mixed with other audio sources to provide the input signals to the motherboard's stereo audio power amplifier. For more information, see Audio System.

Each analog line output signal is obtained from the output of a 24-bit stereo audio DAC, capable of operating at sampling rates from 4kHz to 216kHz. The sampling rate is determined by the Speed mode setting, programmable through an internal register. The same selected speed mode applies to both DAC and ADC circuitry.

Digital volume control is also provided, under control of SPI-accessible control registers. The gain of each channel can be varied from 0dB to -127dB, in 0.5dB steps. Control bits can also be set to mute either channel independently.

Digital Audio I/O

Digital audio data samples are transferred between the CS4270 and a processor in the FPGA design over a 4-wire I2S bus. Both bit and word clock signals (AUDIO_I2S_BCLK and AUDIO_I2S_WCLK) are sourced from the FPGA design, specifically from an intermediate I2S Controller. They are wired to the CODEC's SCLK and LRCK inputs, respectively.

An additional clock signal from the FPGA design – AUDIO_I2S_MCLK – is used to provide the driving frequency for the delta-sigma modulator and digital filters. Wired to the CODEC's MCLK input, the frequency of the AUDIO_I2S_MCLK signal is fixed at 256 times the frequency of the AUDIO_I2S_WCLK signal.

Digital audio data from the processor is passed through the DAC for each channel, in order to produce the analog audio line output signals, for subsequent use as input to the motherboard's audio system.

Digital audio data destined for the processor is obtained by passing the analog audio input signals (LineIn_R, LineIn_L) through a 24-bit stereo audio ADC. Supported sampling rates are the same as for the DACs. The Speed mode, programmable through an internal register, is the same for both ADC and DAC circuitry.

Control bits can also be set to mute each channel independently.

Audio Control Registers

Internal registers for the CS4270, which are used to determine the required functionality of the device, are accessed by a processor in the FPGA design over the SPI bus. These registers, referred to as the Control Port registers, can only control the device provided it is set to operate in Control Port mode. This is achieved after power-up of the NanoBoard by initiating SPI communications within 10ms of the device's RST line going High. The recommended start-up procedure after RST goes High is:

• Set the PDN bit in the Power Control register (at address 02h)
• Wait 1ms
• Clear the PDN bit in the Power Control register
• Wait a further 1ms
• Then continue reading/writing other Control Port registers over the SPI bus.

The following registers should be written, as a minimum, when initializing the device for operation:

• Mode Control register (address 03h) – should be written with the required functional mode and MCLK clocking ratios. The default value for this register is 30h which will select Slave Mode, with divide-by-1 for the clocking ratios.
• ADC and DAC Control register (address 04h) – should be written with the required digital interface formats for both ADC and DAC. A value of 09h, for example, will set both the DAC digital interface format and the ADC digital interface format to be I2S, up to 24-bit data.
• Transition Control register (address 05h) – should be written with the required transitional control functionality. The default value for this register is 60h, which enables both soft ramp and zero cross functions.
• Mute Control register (address 06h) – should be written with the required muting functionality. The default value for this register is 20h, which will enable the CODEC's auto-mute function. In this state, the DAC output will be muted automatically following the reception of 8192 consecutive audio samples of static 0 or -1. The mute will be released on detection of a single non-static sample of audio.
• DAC Channel A Volume Control register (address 07h) – should be written with the volume gain required for the Right channel audio DAC. The default value for this register is 00h, which sets the gain to 0dB.
• DAC Channel B Volume Control register (address 08h) – should be written with the volume gain required for the Left channel audio DAC. The default value for this register is 00h, which sets the gain to 0dB.

For detailed information on all audio control registers, including bit descriptions, refer to the Register Description section of the device's data sheet.

Location on Board

• The CS4270 device (designated U1) is located on the component side of the board, to the left of the peripheral board connector ('NANOCONNECT' interface).
• The MAX6315 device (designated U45) is located on the solder side of the board, to the right of the LDO adjustable regulator for the board's 3.3V power supply (U41).
• The TC1017R device (designated U44) and related circuitry is also located on the solder side of the board, above the LDO adjustable regulator for the board's 3.3V power supply (U41).

TC1017R (U44) and MAX6315 (U45).

Schematic Reference

The audio codec circuitry can be found on the following sheets of the motherboard schematics:

• Sheet 72 (Audio_Codec.SchDoc, entitled Audio CODEC)
• Sheet 73 (AUDIO_CODEC_CS4270.SchDoc, entitled Audio CODEC)
• Sheet 9 (PSU_TC1017R_3V3.SchDoc, entitled PSU TC1017R 3V3)

Design Interface Component

The following table summarizes the available design interface component that can be placed from the FPGA NB3000 Port-Plugin.IntLib, for communications with the stereo audio codec over the I2S bus.

To enable a host processor in your FPGA design to control operation of the CS4270 device, you need to place the design interface component that allows communications with the device over the SPI bus, as summarized in the following table.

Further Device Information

• For more information on the CS4270 device, refer to the datasheet (CS4270_PP1.pdf) available at www.cirrus.com.
• For more information on the MAX6315 device, refer to the datasheet (MAX6315.pdf) available at www.maxim-ic.com.
• For more information on the TC1017R device, refer to the datasheet (21813d.pdf) available at www.microchip.com.