EP2C35F672C8 - Feature Summary
The EP2C35F672C8 device is a member of the 1.2V Cyclone II family of FPGAs. The Cyclone II provides a low-cost, high-density solution for applications such as those targeted to the consumer electronics industry.
The entire Cyclone II family includes nine devices offering densities ranging from 4,608 to 68,416 Logic Elements. The EP2C35F672C8 offers 33,216 Logic Elements. Table 1 provides an information summary for this device.
In order to use the Cyclone II device, you will need to install the relevant Vendor tools – Altera® Quartus® II from www.altera.com. The Altera Quartus II Web Edition Software can be freely downloaded and does not require a license.
Feature | Description |
---|---|
Device Name | EP2C35F672C8 |
Vendor | Altera |
Family | Cyclone II |
Package | 672-Pin FineLine Ball Grid Array (FBGA) |
Speed Grade | 8 |
Temperature Grade | Commercial |
Pin Count | 672 |
Maximum User I/O Pins | 475 |
Max. Differential I/O Pairs | 201 |
Altera Logic Elements | 33,216 |
Embedded (Block) RAM | 483,840 bits (105 M4K RAM blocks: 4096 memory bits |
Embedded Multipliers (18x18) | 35 (each configurable as 9x9 multipliers) |
Clock Managers (PLLs) | 4 |
Global Clock Resources | 16 |
Configuration Memory Required | 6,858,656 bits |
On-Chip Termination Support | Yes |
Location on Board
The Cyclone II device (designated U1
) is located on the component side and in the lower half of the board.
Schematic Reference
The Cyclone II device and related circuitry can be found on the following sheets of the daughter board schematics:
DEVICES.SchDoc
(entitled FPGA, LEDs and SRAM Memory)
FPGA.SchDoc
(entitled FPGA Connections)
FPGA_NonIO.SchDoc
(entitled FPGA Power and Programming)
Bypass_FPGA_1V2.SchDoc
(entitled FPGA Bypass Capacitors for 1V2)
Bypass_FPGA_3V3.SchDoc
(entitled FPGA Bypass Capacitors for 3V3).
Further Device Information
For more information on the EP2C35F672C8 device, refer to the Cyclone II Device Handbook (cyc2_cii5v1.pdf
) available at www.altera.com.