Daughter Board Independent SRAM

The daughter board includes independent Static RAM as part of the memory resources available to the FPGA device, or more specifically the design running within. The term 'independent' is used in this case to distinguish this SRAM – which is interfaced using dedicated address and data lines – from the SRAM that is accessed over a common bus (also used to access on-board SDRAM and Flash memory).

The SRAM is provided in the form of two 4Mbit, high-speed CMOS SRAM devices. Each device is organized as 256K x 16 bits and powered by the daughter board's 3.3V supply.

The devices are accessed separately, giving two distinct 256K x 16-bit storage areas (512KByte each, 1MByte in total).

Although the devices require 18 address lines (SRAM_A[17..0]), the interface makes provision for a nineteenth address line (SRAM_A18), giving the daughter board the flexibility to accommodate 512 x 16-bit devices, should they require to be fitted.

Location on Board

The independent SRAM device on the component side of the board is located towards the bottom-right corner.

Figure 1. Independent SRAM on
the component side (as seen on
the DB30).

The independent SRAM device on the solder side of the board is located towards the bottom-left corner.

Figure 2. Independent SRAM on
the solder side (as seen on the
DB30).

Schematic Reference

The independent SRAM device can be found on sheet SRAM_256Kx16_TSOP44.SchDoc (entitled 256K x 16-Bit SRAM) of the daughter board schematics.

Design Interface Component

Table 1 summarizes the available design interface components that can be placed from the FPGA DB Common Port-Plugin.IntLib for access to, and communications with, the independent SRAM on the daughter board.