Bootstrapping the Daughter Board FPGA on the NanoBoard-NB1
The NanoBoard-NB1 provides the ability to bootstrap the FPGA device located on the currently inserted daughter board, at power-up.
An 8MBit Flash memory device(M25P80) is used to store the programming file required for implementing the design within the FPGA. This device is component U6 on the NB1 motherboard.
The Flash memory is controlled by the NanoTalk Controller – a Xilinx Spartan 100 FPGA.
Running the Flash Memory Controller
The procedure for loading the FPGA programming file into the Flash memory can be carried out at any time – with or without an FPGA project open and irrespective of whether a design has currently been programmed into the target FPGA device (on the daughter board).
From the Devices view, simply double-click on the icon for the NanoBoard whose associated FPGA Boot Flash memory you wish to load.
Figure 1. NanoBoard-NB1
Controller icon.
The Instrument Rack for the NanoBoard Controllers will appear as shown in Figure 2.
Figure 2. NanoBoard Controllers Instrument Rack.
If you have multiple NanoBoards daisy-chained together, the NanoBoard chain will reflect each detected (powered-up) board. Each NanoBoard Controller in the chain will only appear in the Instrument Rack after its corresponding icon has been specifically double-clicked.
On the instrument panel of the required NanoTalk Controller, click on the FPGA Boot button. The Flash RAM Controller For FPGA Boot dialog will appear (Figure 3).
Figure 3. Flash Memory Controller for FPGA Boot dialog.
From this dialog, press the Read Electronic Signature button. This tests the communications link between the NanoTalk Controller and the Flash memory device. If communications are successful, a value will be entered into the field to the immediate right of the button and the confirmatory message Device Found: M25P80 (8M-Bit Serial Flash RAM) will be displayed.
Erasing the Flash Memory
Before loading the required programming file into the Flash memory device, the memory must first be cleared. To erase the entire 8MBit of flash memory, press the Erase Entire Device button in the Flash RAM Controller for FPGA Boot dialog. The erasing process will take approximately 5 seconds.
Programming the Flash Memory
Once the Flash memory has been erased, the programming file can now be downloaded. From the Flash RAM Controller for FPGA Boot dialog, press the ... button (located at the top-right of the dialog). The Choose FPGA Programming File for Download dialog appears. This dialog allows you to browse for and open the required programming file. The programming file for a specific target FPGA device can be found in the corresponding \Out\ConfigurationName sub-folder, for the FPGA project.
When using Xilinx FPGA devices, the programming file used will be different for JTAG programming and Slave-Serial programming. The Flash memory uses the latter when loading the FPGA device on the daughter board. Therefore, when choosing the programming file, the version of the file with the _cclk.bit extension should be used (instead of the file with the .bit extension).
After choosing the file and clicking Open, you will be returned to the Flash RAM Controller for FPGA Boot dialog. The chosen file (including path) will be displayed. To download this file to the Flash memory, simply click the Save File To Flash button.
The download process will proceed, with progress shown in Altium Designer's Status bar. At the end of the download, which takes approximately 15-20 seconds for a Xilinx Spartan IIE-300 device, an information dialog will appear confirming the end of the process.
Verification of Download to Flash Memory
After you have downloaded the FPGA programming file to the Flash memory device, a check should be made to ensure the integrity of the programming file. To do this, from the Flash RAM Controller for FPGA Boot dialog, click on the Verify against File button.
The contents of the Flash memory are read back and compared against the original programming file. The progress for this process is again shown in Altium Designer's Status bar and, for a Xilinx Spartan IIE-300 device, typically takes around 15-20 seconds to complete.
An information dialog will appear with details of the verification results. If the download process is shown to have failed, the verification will report an error count. A large number of errors typically indicates that the Flash memory device was not successfully erased prior to download of the programming file. In this case, try erasing the device again – using the Erase Entire Device button – and then using the Blank Check button (in the same dialog) to verify that the device's memory has indeed been successfully erased. The programming file can then be downloaded again.
Booting the FPGA using the Flash Memory
Once the Flash memory has been successfully programmed with the required FPGA programming file, the FPGA device on the daughter board can now be booted directly from the Flash memory.
Firstly, turn off the NanoBoard. Then insert a jumper at position JP2 - AUTO LOAD FPGA on the NanoBoard (the left-most jumper in the sequence of jumpers located below the VGA interface).
When the NanoBoard is powered-up, the FPGA on the daughter board will be programmed using the file resident in the Flash memory and the design will start running. Depending on the FPGA device used, this startup process can take between 0.2 - 1.0 seconds.