Accessing Common-Bus Memory on a 3-Connector Daughter Board

Frozen Content

Modified by Admin on Nov 6, 2013

Table 1 summarizes the available design interface components that can be placed from the FPGA DB Common Port-Plugin.IntLib for access to, and communications with, any or all of the common-bus memory resources on a 3-connector daughter board.

Table 1. Common-bus memory port-plugin components.

Component Symbol	Component Name	Description
	`SHARED_SRAM_DAUGHTER`	Place this component to interface to the daughter board's common-bus SRAM.
	`SHARED_SDRAM_DAUGHTER`	Place this component to interface to the daughter board's common-bus SDRAM.
	`SHARED_FLASH_DAUGHTER`	Place this component to interface to the daughter board's common-bus Flash memory.
	`SHARED_SRAM_SDRAM_DAUGHTER`	Place this component to interface to the daughter board's common-bus SRAM and SDRAM.
	`SHARED_SRAM_FLASH_DAUGHTER`	Place this component to interface to the daughter board's common-bus SRAM and Flash memory.
	`SHARED_SDRAM_FLASH_DAUGHTER`	Place this component to interface to the daughter board's common-bus SDRAM and Flash memory.
	`SHARED_MEM_DAUGHTER`	Place this component to interface to all of the daughter board's common-bus memory resources.

Only ONE common-bus related port component can be placed in an FPGA design. The design interface component used will depend on which particular memory resource(s) you wish to access, and how you have configured the Shared Memory Controller – the intermediate design peripheral that sits between a processor in the design and the common-bus memory on the daughter board.

The Shared Memory Controller has an option to control the visibility of unused pins – in terms of its physical memory interface. By default, this option is enabled and all pins of the interface will be shown. In terms of wiring, it is more convenient to leave all interface pins visible and wire all pins to the corresponding ports of the SHARED_MEM_DAUGHTER port component. Those signals not required for the design, in accordance with the Controller's configuration, are internally handled. For example, active Low outputs relating to unused memory types are tied to '1', unused inputs are ignored and, if not using the SDRAM, the associated clock output signal will be tied to '0'.

However, you may not be using all three memory types in your design, or may prefer to hide the 'clutter' of pins associated with memory types that are not being used. You would then place the port component that truly corresponds to the memory you are wishing to access, only wiring from the Shared Memory Controller to those pins of relevance. For the remaining pins of the port component chosen, use the orange guidance text on each unused port to terminate it correctly:

VCC – connect the unused port to VCC

GND – connect the unused port to GND

X – place a No ERC directive on the unused port.