XC3SD1800A-4FGG676C - Supported Differential IO Standards

Frozen Content

The following table lists the differential I/O standards supported by the XC3SD1800A-4FGG676C device.

Table 1. Supported differential I/O standards.
I/O Standard
Description

BLVDS_25

Bus Low-Voltage Differential Signaling (2.5V)

DIFF_HSTL_I_18

Differential High-Speed Transceiver Logic (1.8V) Class I

DIFF_HSTL_II_18

Differential High-Speed Transceiver Logic (1.8V) Class II

DIFF_HSTL_III_18

Differential High-Speed Transceiver Logic (1.8V) Class III

DIFF_SSTL18_I

Differential Stub Series Terminated Logic (1.8V) Class I

DIFF_SSTL18_II

Differential Stub Series Terminated Logic (1.8V) Class II

DIFF_SSTL2_I

Differential Stub Series Terminated Logic (2.5V) Class I

DIFF_SSTL2_II

Differential Stub Series Terminated Logic (2.5V) Class II

DIFF_SSTL3_I

Differential Stub Series Terminated Logic (3.3V) Class I

DIFF_SSTL3_II

Differential Stub Series Terminated Logic (3.3V) Class II

LVDS_25

Low-Voltage Differential Signaling (2.5V)

LVDS_33

Low-Voltage Differential Signaling (3.3V)

LVPECL_25

Low-Voltage Positive Emitter-Coupled Logic (2.5V)

LVPECL_33

Low-Voltage Positive Emitter-Coupled Logic (3.3V)

MINI_LVDS_25

Mini Low-Voltage Differential Signaling (2.5V)

MINI_LVDS_33

Mini Low-Voltage Differential Signaling (3.3V)

PPDS_25

Point-to-Point Differential Signaling (2.5V)

PPDS_33

Point-to-Point Differential Signaling (3.3V)

RSDS_25

Reduced Swing Differential Signaling (2.5V)

RSDS_33

Reduced Swing Differential Signaling (3.3V)

TMDS_25

Transition Minimized Differential Signaling (2.5V)

TMDS_33

Transition Minimized Differential Signaling (3.3V)

For more information, refer to the Spartan-3 Generation FPGA User Guide (ug331.pdf), available at www.xilinx.com.

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