Updating the Firmware on the NanoBoard-NB1

The NanoBoard firmware is the program that is loaded into the NanoTalk Controller when the board is powered-up. The NanoBoard-NB1 uses a Xilinx Spartan IIE-100K device (XC2S100E) as the controller for the board. Referred to as the NanoTalk Controller, this device (U8 on the board) manages JTAG communications with the following:

• FPGA Daughter Board

• Master/Slave daisy-chain

• User Board connectors (A and B)

• Flash RAMs (U6 and U7)

• The SPI Master clock.

The NanoTalk Controller also manages the following two areas of the board:

• LEDs SL1-SL8

• The following jumpers on JP2:
   
  • AUTO LOAD FPGA
  • CLOCK0
  • CLOCK1
  • CLOCK2
  • USER A - BYPASS SOFT
  • USER B - BYPASS SOFT
  • TEST 0
  • TEST 1

The firmware that is loaded into the NanoTalk Controller is stored in a Xilinx Serial PROM device (XCF01S). This is U5 on the board. On power-up, the firmware is automatically loaded into the NanoTalk Controller.

The following sections detail the procedure for updating this firmware.

Pre-Update Preparation

Before the new version of firmware can be downloaded to the Serial PROM, the NanoBoard must first be prepared as follows.

1. Turn off the NanoBoard.
    
2. Remove any FPGA Daughter Board that is currently plugged in.
    
3. Insert a jumper at JP2 - SYSTEM JTAG on the NanoBoard (to the bottom left of the parallel cable connector). This is a fixed function jumper which, when inserted, switches control of the NanoBoard from the NanoTalk Controller (Spartan IIE-100K) to a simple hardware chain, which involves the NanoTalk Controller and the Xilinx Serial PROM.
    
4. Power-up the NanoBoard.

Erasing the PROM

Within Altium Designer, open the Devices view, if not already open. Ensure that the Live check box is checked as this enables the auto-board-recognition system.

With the jumper inserted, the Xilinx Serial PROM device will appear in the Hard Devices chain, as shown in Figure 1.

Figure 1. Accessing the Serial PROM device.

The Xilinx Serial PROM is a Flash memory device. Before it can be programmed with the new firmware, it must first be cleared. To do this, right-click on its icon in the Hard Devices chain (Platform Flash) and choose Reset Hard Device from the pop-up menu.

The erasing process will proceed, with progress shown in Altium Designer's Status bar. The process takes approximately 15 seconds to complete.

Downloading the New Firmware

The configuration for the Xilinx Serial PROM device is stored in a PROM file, using the Intel MCS-86 format. This is an ASCII hex file with extension .mcs.

To download the new configuration, right-click on the icon for the PROM in the Hard Devices chain of the Devices view and select Choose File and Download from the pop-up menu.

The Choose Programming File For Xilinx XCF XCF01SSVO20C dialog appears. Use this dialog to navigate to the required programming file (.mcs) and click *Open. By default, this file is located in the \System folder of the installation.

A confirmation dialog will appear, asking whether you wish to verify the programming (of the PROM). At this stage, the new firmware has not been downloaded. Click Yes to proceed with the download and verification cycle.

The download and verification will take approximately 30-40 seconds to complete. The progress is shown in Altium Designer's Status bar. At the end of the cycle, an information dialog will appear with the result of the download.

If any errors occur during the download and verification cycle, a warning dialog will appear. If this happens, power-down the NanoBoard for a few seconds and then run the whole process again – including the erasure of the PROM device's memory.

Testing the NanoBoard

Once the Xilinx Serial PROM device has been successfully programmed, the new firmware can be tested as follows:

1. Power-down the NanoBoard and plug-in an FPGA daughter board.
    
2. Remove the jumper from JP2 - SYSTEM JTAG.
    
3. Power-up the NanoBoard.
    
4. Ensure that the Live check box (at the top left of the Devices view) is checked to enable the auto-board-recognition system.
    
5. In the Devices view, press F5 (Refresh). This forces a scan of the hardware to detect which devices are currently connected. The NanoTalk Controller for the connected NanoBoard will automatically be detected and appear in the NanoBoard chain. The version of the firmware currently being used by the Controller is reflected beneath the Controller's icon (e.g. V1.1.18). The FPGA device on the daughter board should be automatically detected and appear in the Hard Devices chain.
    
6. Open an FPGA project that includes Nexus-enabled devices (e.g. Microprocessors, Counters, Logic Analyzers) and program the FPGA on the daughter board. This will test that the Soft Devices chain is functioning correctly.
    
   
   Figure 2. Target FPGA device detection and test of the Soft Devices chain.
    
7. With the chosen design running in the FPGA, double-click on the icon for the NB1 (in the NanoBoard chain of the Devices view). The Instrument Rack for the NanoBoard Controllers will appear. Use the Instrument Panel to change the system clock frequency. This will write the new clock frequency to the system clock which, being an SPI device, will test that communication to SPI devices is working correctly.
    
   
   Figure 3. Use the instrument panel for the NanoBoard to change the clock frequency of the SPI-based programmable clock.
    
   As well as writing the new frequency to the clock, the value will also be stored in the NanoTalk Controller and will be read back to verify the change. The new frequency is persistent across design sessions with respect to the software, but not persistent across hardware sessions. Therefore, closing the application, relaunching and opening an FPGA project will result in the last clock frequency entered being used. However, cycling the power on the NanoBoard will result in the default clock frequency (50MHz) being used because the register used to store the chosen clock frequency in the NanoTalk Controller is cleared on power-down.