TFT LCD Panel - Bootstrapping the Daughter Board FPGA

The Desktop NanoBoard NB2DSK01 provides the ability to bootstrap the physical FPGA device, on the currently inserted daughter board, at power-up.

To access boot controls (Figure 1), from the Home screen of the GUI touch the icon, followed by the icon.

Figure 1. Controls related to bootstrapping of the
FPGA device.

The GUI allows you to choose whether or not you wish to enable use of the boot feature and, if so, from where the programming file(s) for the design will be sourced for the boot process – either from an SD memory card inserted into the NB2DSK01 motherboard's SD card reader, or from dedicated on-board SPI Flash memory.

Booting from an SD Card

To boot from an SD memory card on power-up, simply use the GUI to select the option First example found on SD-card, and ensure the SD memory card carrying the design is inserted into the motherboard's SD card reader (designated J8 on the board).
 

 
Once the NB2DSK01's power is cycled, the first EXAMPLE file found will be used (EXAMPLE files are sorted alphabetically). This will also depend on the file structure in-place on the card. The FPGA programming file referenced in the EXAMPLE file will be downloaded to the daughter board FPGA. Any HEX file referenced will be downloaded to the M25P80 SPI Flash memory device that is solely used for embedded storage purposes (designated U20 on the motherboard).

Booting from SPI Flash Memory

To boot using a design stored in serial Flash memory, simply use the GUI to select the Serial Flash option and ensure that the FPGA programming file for the design is loaded into the M25P80 SPI Flash memory device that is used for boot purposes (designated U21 on the motherboard). Once the NB2DSK01's power is cycled, the FPGA programming file stored in the SPI Flash memory will be downloaded to the daughter board FPGA.

The procedure for loading an FPGA programming file into the Flash memory can be carried out at any time – with or without an FPGA project open and irrespective of whether a design is currently programmed into the target FPGA device (on the daughter board).

Controls for downloading to, and erasing, the Flash memory, can be found in the Flash RAM Controller For FPGA Boot dialog. Access to and use of this dialog, is detailed in the following sections.

Accessing Flash Memory Controls

The Flash RAM Controller For FPGA Boot dialog is accessed directly from the instrument panel for the NB2DSK01's NanoTalk Controller. From the Devices view (View » Devices View), simply double-click on the icon for the NanoBoard (in the NanoBoard Controllers chain) whose FPGA Boot Flash memory you wish to load. The Instrument Rack - NanoBoard Controllers panel will appear. Click on the FPGA Boot Flash button to access the dialog (Figure 2).

Figure 2. Accessing controls for the FPGA Boot Flash memory.

The Device ID region of the dialog reflects the communications link between the NanoTalk Controller and the Flash memory device. If communications are successful, upon accessing the dialog a value of $13 will be entered into the far right field and the confirmatory message "Device Found: M25P80 (8M-Bit Serial Flash RAM)" will be displayed. If this is not the case, try to manually interrogate the communications link by pressing the Read Electronic Signature button.

Erasing the Flash memory

Before loading the required programming file into the Flash memory device, the memory must first be cleared. To erase the entire 8Mbit of Flash memory, press the Erase Entire Device button, in the Erase region of the Flash RAM Controller For FPGA Boot dialog. The erasing process will take approximately five to eight seconds, after which a confirmation dialog will appear (Figure 3).

Figure 3. Confirming full erasure.

Controls are also available for erasing a particular sector of memory. Each M25P80 device is organized into 16 sectors. Each sector contains 256 pages, and each page is 256 bytes wide. Therefore each sector is 65536 bytes or 512Kbits.

Simply use the available drop-down to select the sector you wish to erase (or enter the sector number directly) and then click the Erase Sector button. Erasure time is typically less than a second, after which time you will receive a dialog to confirm completion of the erase (Figure 4).

Figure 4. Sector erasure.

To verify that the device has been successfully erased, press the Blank Check button. The verification process will take approximately sixty seconds, after which time you will receive another confirmation dialog (Figure 5).

Figure 5. Verification of memory erasure.

Downloading to Flash Memory

Once the Flash memory has been erased, the programming file can be downloaded. From the Download region of the Flash RAM Controller For FPGA Boot dialog, press the ... button to the right of the File Name field. The Choose FPGA Programming File For Download dialog will appear. Use this dialog to browse to, and open, the required file. The programming file used depends on the target device:

• *.bit file for a Xilinx device

• *.rbf file for an Altera device

• *.rbt (ASCII) or *.bit (binary) file for a Lattice device

• *.stp file for an Actel device.

 
For a design that has been compiled, synthesized and built using Altium Designer, the programming file will be located in the {OutputPath}\ConfigurationName sub-folder defined for the project. The {OutputPath} is project-specific and is defined on the Options tab of the Options for FPGA Project dialog (Project » Project Options). ConfigurationName is the configuration containing a constraint file that targets the physical FPGA device on the daughter board, into which the design will be programmed. For example NB2DSK01_08_DB30_06, which targets the Xilinx Spartan-3 device on the DB30.

After choosing the file and clicking Open, you will be returned to the Flash RAM Controller For FPGA Boot dialog. The chosen file (including path) will be displayed in the File Name field (Figure 6).

Figure 6. FPGA programming file chosen and ready for download.

To download this file to the Flash memory device, simply click the Save File To Flash button. If you want to download to a specific area of memory, enter the required address in the Memory Address field. The download process will proceed, with progress shown in Altium Designer's Status bar. At the end of the download an information dialog will appear, confirming the end of the process (Figure 7).

Figure 7. Confirmation of file download to the Flash memory device.

Verifying the Download

After you have downloaded the FPGA programming file to the Flash memory device, a check should be made to ensure the integrity of the file. To do this, simply click on the Verify against File button, in the Download region of the Flash RAM Controller For FPGA Boot dialog.

The contents of the Flash memory are read back and compared against the original programming file. Progress is again reflected in Altium Designer's Status bar. An information dialog will appear at the end of the process, providing details of the verification results (Figure 8).

Figure 8. Successful verification of downloaded
file.

If the download process is shown to have failed, the dialog will report an error count. A large number of errors typically indicates that the Flash memory device was not successfully erased prior to downloading the programming file. In this case, try erasing the device again – using the Erase Entire Device button – and then using the Blank Check button to verify that the device's memory has indeed been successfully erased. The programming file can then be downloaded again.