PB03 Resources - Ethernet Port
The PB03 provides a fast Ethernet connection, supporting 100Base-TX and 10Base-T, for operational speeds of up to 100Mbps and 10Mbps respectively.
An 8P8C ('RJ45') modular connector is used to provide the Ethernet port. Connection to the external network is made using standard Category 5 (Category 5e) unshielded twisted pair (UTP) network cable.
Figure 1. 10/100 Ethernet
interface port.
Providing the interface between an Ethernet Media Access Controller in an FPGA design and the external network, is an RTL8201CL 10/100M Fast Ethernet PHYceiver device (from Realtek).
Powered from the PB03's 3.3V supply, the device provides an MII (Media Independent Interface), with which communications with an FPGA-based MAC device are performed. Not only is this interface used to send and receive network data to and from a processor in the design, it also provides management signals for configuring the PHYceiver device. To use this interface, the device has been set to operate in MII mode by tying its MII/SNIB pin High.
External 4K7Ω pull-down resistors on the CRS and RXER lines ensure that at power-up/reset, the device is configured for normal operation and for communication over UTP cabling. A standard buffer (SN74LVC244ADB) is used to ensure the effectiveness of these resistors.
The MII interface can operate at a frequency of 25MHz or 2.5MHz (providing the Transmit and Receive clock signals to the MAC device in the FPGA design), to support 100Mbps and 10Mbps bandwidths respectively. The clock signal is supplied from an internal PLL, which itself is driven by an external 25MHz crystal connected across the device's X1 and X2 pins.
The RTL8201CL device supports auto-negotiation with other transceivers, in accordance with IEEE 802.3. The device's ANE, SPEED and DUPLEX pins have been tied High, enabling auto-negotiation and giving the device the ability to freely choose between 10Base-T/100Base-TX and half/full duplex mode combinations, as required by the outcome of a negotiation.
The device's isolation and repeater modes have been disabled by tying the respective ISOLATE and RPTR pins to GND.
The device has also been hardwired to operate in LDPS (Link Down Power Saving) mode, by tying its LDPS pin High. In this mode, the device essentially monitors the status of the link. If the link is down, the transmit function will be ceased, giving an average 70% power saving.
The RTL8201CL can be reset in two ways:
- Hardware Reset – this is achieved by taking the
ETH_RESETB_Esignal (from the FPGA design) Low. This reset signal is generated by the MAC device in the design, which in turn is the logical NOT of the hard reset signal issued to that MAC device. Therefore resetting the MAC will cause a reset of the PHYceiver.
- Software Reset – this is achieved by writing a '1' to the reset bit of the PHYceiver's Basic Mode Control Register (Register 0).
Pins 9, 10, 12, 13 and 15 of the device (LED0/PHYAD0..LED4/PHYAD4) have a dual nature. Upon power-up/reset, their respective levels are latched-in to define the address of the PHYceiver device. The RTL8201CL on the PB03 is set to have the binary address 00001 – PHYAD0 being the LSB.
During normal operation, these five pins are used for driving the following status indication LEDs:
'Link'(LED0, Red) – reflects the status of the link. This LED is lit when the PHYceiver device is linked to another device on the network.
'Full Duplex'(LED1, Red) – reflects the duplex state. This LED is lit when operating in Full Duplex mode.
'10M'(LED2, Green) – this is the 10Mbps activity LED. It is lit when the PHYceiver device is linked in 10Base-T mode, and blinks when data is being transmitted or received.
'100M'(LED3, Green) – this is the 100Mbps activity LED. It is lit when the PHYceiver device is linked in 100Base-TX mode, and blinks when data is being transmitted or received
'Collision'(LED4, Red) - used to indicate a collision. This LED will blink when collisions are encountered.
Figure 2. Ethernet status LEDs.
Sitting between the PHYceiver's network interface and the Ethernet port is a TS6121C 10/100Base-T Ethernet Isolation Transformer (from Bothhand USA).
Location on Board
The Ethernet connector (designated J1_E) is located toward the lower-left corner, on the component side of the board – to the left of the IrDA interface.
The RTL8201CL device (designated U1_E), the TS6121C device (designated T1_E) and the 244 octal buffer (designated U2_E) are also located on the component side of the board, above the Ethernet port itself.
The 25MHz crystal (designated Y1_E) is located on the component side of the board, to the top-right of the Ethernet connector.
The status LEDs (LED0 - LED4) are located along the left-hand edge of the board, with LED4 in the topmost position.
Figure 3. Ethernet PHYceiver device (U1_E),
Ethernet isolation transformer (T1_E), buffer (U2_E)
and 25MHz crystal (Y1_E).
Schematic Reference
The Ethernet circuitry can be found on sheet Ethernet_RTL8201CL.SchDoc (entitled Ethernet Interface) of the peripheral board schematics.
Design Interface Component
Table 1 summarizes the available design interface component that can be placed from the FPGA PB03 Port-Plugin.IntLib to access the Ethernet interface.
| Component Symbol | Component Name | Description |
|---|---|---|
| ETH_PHY | Place this component to access the RTL8201CL PHYceiver device and subsequent Ethernet port. |
Further Device Information
For more information on the RTL8201CL device, refer to the datasheet (spec-8201cl(124).pdf) available at www.realtek.com.tw.
For more information on the TS6121C device, refer to the datasheet (TS6121C-RevB3-030729.pdf) available at www.bothhandusa.com.