NanoBoard 3000 - Test-Reset Button

Frozen Content

The NanoBoard 3000 provides a push button switch that is wired to an I/O pin of the User FPGA. The button has no intrinsic function – it is simply a switch made available for FPGA design purposes. It is typically used to provide the external reset signal (RST_I) for an FPGA design. As such, it is labeled on the board as 'TEST/RESET'.

Provide an external reset to your
design using this dedicated
Test/Reset button.

The switch is of type SPNO – Single Pole Normally Open. In the open position, it provides a logical High signal to the User FPGA, changing to logical Low when pressed.

Location on Board

The switch (designated SW6) is located on the component side of the board, to the left of the 'RGB USER LEDS'.

Schematic Reference

The switch circuitry can be found on Sheet 64 (SW_RESET_SPNO.SchDoc, entitled Push Button SPNO Switch) of the motherboard schematics.

Design Interface Component

Table 1 summarizes the available design interface component that can be placed from the FPGA NB3000 Port-Plugin.IntLib, to access and use the push button switch, SW6.

Table 1. Test/Reset switch port-plugin component.


Component Symbol



Component Name






Place this component to interface to, and use, the push button switch (SW6) in your FPGA design.

As the signal is normally High (switch open) and the RST_I signal is active High, an inverter is typically placed directly in front of the interface component (within the FPGA design), therefore preventing a permanent reset signal.

For more information on the inverter and other generic components available for use in an FPGA design, refer to the FPGA Generic Library Guide.





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