NanoBoard 3000 - System Clocks

Frozen Content

The NanoBoard 3000 has an SPI-based system clock generator (an ICS307-02 device) that provides a fixed 20MHz clock and a user-programmable clock providing frequencies from 6 to 200 MHz. Both clocks are made available to the NanoTalk Controller and the User FPGA, connected to FPGA GCLK pins.

NanoBoard clock circuitry
(fixed and programmable clocks).

The user-programmable clock has a default frequency of 50 MHz. It can be programmed in one of two ways:

  • From a PC with Altium Designer using the instrument panel for the NanoTalk Controller. This allows frequency presets to common values, as well as any frequency possible with the ICS clock device.
  • By the User FPGA application at run time, via the NanoTalk Controller-to-User FPGA SPI interconnect.

Location on Board

The ICS307-02 device (designated U2) is located on the component side of the board, along with the 20MHz surface mount crystal (designated Y1) which is used to provide the fixed reference frequency. Both can be found below the common-bus Flash memory device (U7).

Schematic Reference

The system clock circuitry can be found on Sheet 21 (CLK_ICS307-02_PLL.SchDoc, entitled Programmable SPI Clock) of the motherboard schematics.

Design Interface Component

Table 1 summarizes the available design interface components that can be placed from the FPGA NB3000 Port-Plugin.IntLib, to access these resources.

Table 1. System clock port-plugin components.


Component Symbol



Component Name






Place this component to bring the motherboard's programmable system clock signal into your FPGA design.


Place this component to bring the motherboard's fixed 20MHz system clock signal into your FPGA design.


Place this component to bring both fixed and programmable system clock signals into your FPGA design, using a single port component.

The programmable clock signal (CLK_BOARD) will typically be used as the CLK_I input to devices in a design. Some peripheral devices used within a design may require input clocks of a particular frequency. This frequency is typically achieved by passing one of the system clocks through one or more clock divider devices.

For more information on the available fixed and programmable clock divider components available for use in an FPGA design, refer to the Functional Classes – Clock Divider section of the FPGA Generic Library Guide.

Further Device Information

For more information on the programmable ICS307-02 device, refer to the datasheet (ics3070102[1].pdf) available at

You are reporting an issue with the following selected text and/or image within the active document: