NanoBoard 3000 - IR Receiver

Frozen Content

The NanoBoard 3000 provides an IR receiver, courtesy of a TSOP32338 device (from Vishay Semiconductors), for implementation of a remote control system within your FPGA design. The device incorporates an Automatic Gain Control (AGC) circuit using Vishay's AGC3™ response algorithm – especially designed for noisy environments and IR data that has been transmitted using a fast coding scheme (short bursts).

Powered by the motherboard's 3.3V supply, this device – which actually resides on the TFT LCD panel satellite board (NB3000-TFT01) – can be used to receive IR data transmitted using a 38kHz carrier frequency – ideally suited to data transmitted using the NEC IR transmission protocol.

IR receiver module.

The NanoBoard 3000 ships with a general purpose remote controller, featuring a range of common function buttons. This controller transmits data using the NEC IR transmission protocol.

General purpose remote
control unit shipped with the
NanoBoard 3000.

In terms of operation of the receiver module, transmitted infrared data from a remote controller is detected by a PIN photodiode and converted into a voltage signal. This signal is then passed through a preamplifier and bandpass filter, the latter of which is used to filter out noise disturbance (i.e. background infrared "noise" emitted by other heat-generating objects and alternate-frequency IR transmitters).

The signal is then demodulated, stripping away the carrier signal and presenting just the encoded data at the output. This signal (IR38KRX) is subsequently wired to an I/O pin of the User FPGA. This signal can then be passed through an infrared decoder peripheral device within the FPGA design and the subsequent decoded data used accordingly by embedded software running on a recipient processor.

The output pin of the receiver module is active Low, meaning that a detected pulse burst (mark) from a transmitter will be reflected at the output of the receiver as a Low signal. Conversely, a period of non-activity (space) from the transmitter will be reflected at the output of the receiver as a High signal.

A separate I/O line from the User FPGA (labeled IR38KTX) is also wired through to the 1.8" ATA/IDE interface connector (J1), located on the TFT LCD panel satellite board (NB3000-TFT01). This signal is currently not used.

Location on Board

The IR receiver module (designated LED1) is located on the satellite PCB (NB3000-TFT01) upon which the TFT LCD panel resides.

Schematic Reference

The IR receiver module can be found on sheet NB3000TFT01.SchDoc (entitled TFT and IR 38kHz Board). A PDF of this schematic can be found in the document NB3000-TFT01 Schematic.pdf.

Design Interface Component

Table 1 summarizes the available design interface component that can be placed from the FPGA NB3000 Port-Plugin.IntLib, to access and use the IR receiver module.

Table 1. IR receiver port-plugin component.
Component Symbol
Component Name


Place this component to interface to, and use, the IR receiver module in your FPGA design.

Further Device Information

For more information on the TSOP32338 device, refer to the datasheet (tsop321.pdf) available at

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