NanoBoard 3000 - Host FPGA (NanoTalk Controller)

Frozen Content

The NanoBoard 3000 uses an FPGA device as the controller for the board. This device is commonly referred to as the Host FPGA, or NanoTalk Controller. It is this device into which the 'smarts' of the system – the NanoBoard firmware – gets loaded upon power-up.

Example NanoTalk Controller on the Xilinx
variant (NanoBoard 3000XN), implemented
using a Xilinx Spartan-3AN device.

The NanoTalk Controller manages JTAG communications with:

  • USB-PC interface
  • User FPGA
  • Peripheral board
  • System JTAG header.

The NanoTalk Controller also manages/communicates with the following areas of the board:

  • 1-Wire memory devices (used for identification) on motherboard and peripheral board
  • Host status LEDs.

and the following SPI-based resources:

  • SPI Master clock
  • Host and User SPI Flash memories
  • Real-Time Clock (RTC)
  • SPI resources on peripheral board
  • Diagnostics interface.

In addition to JTAG chain management and communications with board resources locally, the NanoTalk Controller multiplexes the various device chains (NanoBoard, Hard JTAG and Soft JTAG) to present a single JTAG link to the PC on which the Altium Designer software is installed. This single chain is then demultiplexed by the software.

Accessing information for the multiplexed JTAG chains over a single JTAG link.

The JTAG link between the NanoBoard 3000 and the PC is implemented using a USB 2.0 port. For more information, see NanoBoard-PC Interface (USB Port).

Location on Board

The Host FPGA device (designated U30) is located on the component side of the board, to the bottom-right of the TFT LCD panel, and above the generic user switches.

Specific FPGA Device used

The actual FPGA device used as the NanoTalk Controller depends on the variant of 3000-series NanoBoard being used:

  • NanoBoard 3000XN – Xilinx variant: A Xilinx Spartan-3AN device (XC3S400AN-4FGG400C) is used. This is a 400-pin device (311 User I/O) with 360K of embedded RAM and 8064 logic cells.
  • NanoBoard 3000AL – Altera variant: An Altera Cyclone III device (EP3C10F256C8N) is used. This is a 256-pin device (182 User I/O) with 414K of embedded RAM and 10320 logic elements.
  • NanoBoard 3000LC – Lattice variant: A LatticeECP2 device (LFE2-12E-5FN256C) is used. This is a 256-pin device (193 User I/O) with 221K of embedded RAM and 12K LUTs.

Schematic Reference

The NanoTalk Controller and associated circuitry, can be found on the following sheets of the motherboard schematics:

  • Sheet 11 (Host_FPGA.SchDoc, entitled Host Controller - Spartan3AN-400)
  • Sheet 12 (HOST_FPGA_NonIO.SchDoc, entitled Host FPGA Pwr and Programming)
  • Sheet 15 (FPGA_Bypass_1V2.SchDoc, entitled FPGA Bypass 1V2)
  • Sheet 16 (FPGA_Bypass_3V3.SchDoc, entitled FPGA Bypass 3V3).

Further Device Information

More information on a host FPGA device can be found through the Browse Physical Devices dialog. Access this dialog from the Devices view (View»Devices View) by choosing the Browse Physical Devices entry in the main Tools menu.

Alternatively, refer to the relevant datasheet for the device:

  • Xilinx Spartan-3AN (XC3S400AN-4FGG400C) – the datasheet (ds557.pdf) and associated user guide (ug331.pdf) available at
  • Altera Cyclone III (EP3C10F256C8N) – the Cyclone III Device Handbook (cyclone3_handbook.pdf) available at
  • LatticeECP2 (LFE2-12E-5FN256C) – the LatticeECP2/M Family Handbook (HB1003.pdf) available at
You are reporting an issue with the following selected text and/or image within the active document: