NanoBoard 3000 - Ethernet Port

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The NanoBoard 3000 provides a fast Ethernet connection, supporting 10Base-T and 100Base-TX, for operational speeds of up to 10Mbps and 100Mbps respectively.

An 8P8C ('RJ45') modular connector is used to provide the Ethernet port (a KMFC0901238, from Konvee). The connector has integrated 10/100Base-T Ethernet Isolation Transformers and two indication LEDs. The latter – one yellow and one green – have been wired to reflect the Link status and 100Mbps activity, respectively. Connection to the external network is made using standard Category 5 (Category 5e) unshielded twisted pair (UTP) network cable.

10/100 Ethernet interface port.

Providing the interface between an Ethernet Media Access Controller in an FPGA design and the external network, is an RTL8201CL 10/100M Fast Ethernet PHYceiver device (from Realtek).

Powered from the motherboard's 3.3V supply, the device provides an MII (Media Independent Interface), with which communications with an FPGA-based MAC device are performed. Not only is this interface used to send and receive network data to and from a processor in the design, it also provides management signals for configuring the PHYceiver device. To use this interface, the device has been set to operate in MII mode by tying its MII/SNIB pin High.

External 4K7Ω pull-down resistors on the CRS and RXER lines ensure that at power-up/reset, the device is configured for normal operation and for communication over UTP cabling. A standard buffer (SN74LVC244ADB) is used to ensure the effectiveness of these resistors.

The MII interface can operate at a frequency of 2.5MHz or 25MHz (providing the Transmit and Receive clock signals to the MAC device in the FPGA design), to support 10Mbps and 100Mbps bandwidths respectively. The clock signal is supplied from an internal PLL, which itself is driven by an external 25MHz crystal connected across the device's X1 and X2 pins.

The RTL8201CL device supports auto-negotiation with other transceivers, in accordance with IEEE 802.3. The device's ANE, SPEED and DUPLEX pins have been tied High, enabling auto-negotiation and giving the device the ability to freely choose between 10Base-T/100Base-TX and half/full duplex mode combinations, as required by the outcome of a negotiation.

The device's isolation and repeater modes have been disabled by tying the respective ISOLATE and RPTR pins to GND.

The device has also been hardwired to operate in LDPS (Link Down Power Saving) mode, by tying its LDPS pin High. In this mode, the device essentially monitors the status of the link. If the link is down, the transmit function will be ceased, giving an average 70% power saving.

The RTL8201CL can be reset in two ways:

  • Hardware Reset – this is achieved by taking the ETH_RESETB_E signal (from the FPGA design) Low. This reset signal is generated by the MAC device in the design, which in turn is the logical NOT of the hard reset signal issued to that MAC device. Therefore resetting the MAC will cause a reset of the PHYceiver.
  • Software Reset – this is achieved by writing a '1' to the reset bit of the PHYceiver's Basic Mode Control Register (Register 0).

Pins 9, 10, 12, 13 and 15 of the device (LED0/PHYAD0..LED4/PHYAD4) have a dual nature. Upon power-up/reset, their respective levels are latched-in to define the address of the PHYceiver device. The RTL8201CL is set to have the binary address 00001PHYAD0 being the LSB.

During normal operation, these five pins are used for driving the following status indication LEDs:

  • 'LINK' (LED3, Green) – reflects the status of the link. This LED is lit when the PHYceiver device is linked to another device on the network.
  • 'FULL DUPLEX' (LED4, Green) – reflects the duplex state. This LED is lit when operating in Full Duplex mode.
  • '10Mbps' (LED5, Yellow) – this is the 10Mbps activity LED. It is lit when the PHYceiver device is linked in 10Base-T mode, and blinks when data is being transmitted or received.
  • '100Mbps' (LED6, Orange) – this is the 100Mbps activity LED. It is lit when the PHYceiver device is linked in 100Base-TX mode, and blinks when data is being transmitted or received
  • 'COLLISION' (LED7, Red) - used to indicate a collision. This LED will blink when collisions are encountered.

Ethernet status LEDs.

Location on Board

The Ethernet connector (designated J8) is located along the top edge on the solder side of the board. Looking from the rear, it can be found to the left of the RS-485 connector.

Ethernet Port (as seen from the rear of the board).

The RTL8201CL device (designated U5), the 244 octal buffer (designated U6), and the 25MHz crystal (designated Y2) are also located on the solder side of the board, below the Ethernet port itself.

Ethernet PHYceiver device (U5), buffer (U6) and 25MHz crystal (Y2).

The status LEDs (LED3 - LED7) are located on the component side of the board, in-between the ADC and PWM screw terminals (J13 and J16), with LED4 in the topmost position.

Schematic Reference

The Ethernet circuitry can be found on the following sheets of the motherboard schematics:

  • Sheet 54 (Ethernet_RTL8201CL.SchDoc, entitled Ethernet Interface)
  • Sheet 55 (CON_ETHERNET_RJ45_LEDS.SchDoc, entitled Ethernet Connector).

Design Interface Component

Table 1 summarizes the available design interface component that can be placed from the FPGA NB3000 Port-Plugin.IntLib to access the Ethernet interface.

Table 1. Ethernet interface port-plugin component.
Component Symbol
Component Name


Place this component to access the RTL8201CL PHYceiver device and subsequent Ethernet port.

Further Device Information

For more information on the RTL8201CL device, refer to the datasheet (spec-8201cl(124).pdf) available at

For more information on the ethernet connector, refer to the datasheet (KMFC0901238.pdf) available at

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