NB2DSK01 Constraint System Overview

Frozen Content

The constraint system in place for the Desktop NanoBoard NB2DSK01 utilizes various constraint files covering:

  • Resources and pin-mapping local to the NB2DSK01 motherboard and satellite peripheral and daughter boards
  • Connection of a satellite board (peripheral boards and daughter boards) to the NB2DSK01 motherboard.

Figure 1 indicates the base set of constraint files used for a design targeting a daughter board FPGA device – plugged into the NB2DSK01 motherboard – and where that design utilizes additional peripherals located across all three plug-in peripheral boards.


Figure 1. Constraint files used for a design targeted to the NB2DSK01.

Table 1 summarizes these base constraint files. Together, they ultimately map the resources available (on motherboard, daughter board and peripheral boards) to the physical pins of the daughter board FPGA.

Table 1. Constraint file descriptions.
Constraint File
Targets
Description
A

Peripheral board PBxx

Defines the peripheral board and its connector, as well as the mapping of all resources on that board to pins of that connector.

B

Peripheral board PBxx

 

C

Peripheral board PBxx

 

D

NB2DSK01 motherboard

Defines the NB2DSK01 motherboard and its connectors (daughter board, peripheral board and user board); the mapping of pins between peripheral board connectors and daughter board connectors; and the mapping of all NB2DSK01 motherboard resources to pins of the daughter board connectors.

E

Daughter board DBxx

Defines the daughter board and FPGA device, the connectors available on that board, and the pin mapping between those connectors and pins of the physical device. The mapping of any other resources on the daughter board, available for use by the FPGA design (e.g. memories), is also specified in this file.

F

Peripheral board-to-motherboard and daughter board-to-motherboard interfaces

Declares the following:

  • NanoBoard instance
  • Daughter board instance
  • Peripheral board instance(s)
  • Daughter board-to-motherboard connector mapping
  • Peripheral board-to-motherboard connector mapping.


  1. Additional constraint files may be included/used, such as a file for timing-related constraints.
     
  2. Constraint file F in Figure 1 and Table 1 is commonly referred to as the 'Board Mapping constraint file'. It does not exist as part of the installation, but rather is created on-the-fly, in accordance with the hardware in the system.
     
  3. Depending on the resources being used by your design and the number of peripheral boards plugged into the NB2DSK01 motherboard, your FPGA project may contain up to three peripheral board-related constraint files, one per board.
     
  4. If your FPGA project has multiple configurations – targeting different daughter board FPGA devices – there will be a daughter board-related constraint file for each different device targeted. The different configurations will contain these different constraint files. A different board mapping constraint file will also be generated for, and assigned to, each unique configuration.

See Also

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