NB2DSK01 - User IO Headers

Frozen Content

Modified by Admin on Sep 13, 2017

The NB2DSK01 includes two I/O headers that allow user-defined hardware to be interfaced to the daughter board FPGA. These 20-pin headers – designated UH1 and UH2 – cater for a total of 36 daughter board FPGA I/O signals, 18 wired to each.

Figure 1. Connect to off-board hardware through use of the NB2DSK01's dedicated
User I/O headers.

Each header also supplies power (pin 1) and ground (pin 20) signals. The power supply level is user-selectable via an associated configurable jumper header – designated JP4 and JP5 respectively. Table 1 summarizes the effect of jumper placement on these headers.

Table 1. JP4/JP5 header jumper placement.

Jumper Position	Description
1-2	Put a jumper on these pins to provide the NB2DSK01's 5V supply.
3-4	Put a jumper on these pins to provide the NB2DSK01's 3.3V supply.

Take care to place only a single jumper on each of headers JP4 and JP5 – to select either 3.3V or 5V in each case. DO NOT put jumpers in both positions for a header simultaneously. The result will be elevation of the 3.3V line to 5V, causing damage to devices expecting a 3.3V supply.

Current monitoring is also in place for the power lines selected.

Location on Board

The two headers, labeled 'User Header A' (UH1) and 'User Header B' (UH2) respectively, are located on the component side of the board, between the 'DAUGHTER BD TEST/RESET' button and the ADC/DAC.

The two configurable jumper headers (JP4 and JP5) are also located on the component side, directly to the left of their respective user headers (UH1 and UH2).

Schematic Reference

The User I/O headers can be found on Sheet 47 (CON_USER_20WBOXHDRRAMx2.SchDoc, entitled 36-Way User I/O Headers) of the motherboard schematics.

Design Interface Component

Since the headers can be configured as either input or output, an associated design interface component is not provided.