NB2DSK01 - User DIP-Switch

Frozen Content

The NB2DSK01 provides an 8-way DIP-switch, with each switch wired to a separate I/O pin of the daughter board FPGA device. This provides you with eight generic switchable signals for use in an FPGA design.

Figure 1. Switchable inputs provided courtesy
of the 8-way DIP-switch.

The DIP-switch is wired as an active low device, which means setting a switch to the ON position generates a corresponding Low signal.

Location on Board

The DIP-switch (designated SW7) is located on the component side of the board, to the immediate right of the User LEDs.

The eight switch signals arrive at the daughter board FPGA as signals DIP0 to DIP7. On the physical device, DIP7 is the signal associated with switch number 1, in the left-most position.

Schematic Reference

The DIP-switch circuitry can be found on Sheet 59 (SW_DIP8.SchDoc, entitled 8-Way DIP Switch) of the motherboard schematics.

Design Interface Component

Table 1 summarizes the available design interface component that can be placed from the FPGA NB2DSK01 Port-Plugin.IntLib, to access and use the DIP-switch.

Table 1. DIP-switch port-plugin component.

 

Component Symbol

 

 

Component Name

 

 

Description

 

DIPSWITCH

Place this component to interface to the NB2DSK01's DIP-switch.

Although the eight signals arrive at the daughter board FPGA device on separate pins, the interface component provides an 8-bit bus input. Connection to the component's bus port depends on where in the design these signals are destined. If, for example, you wish to control port input to an 8-bit wide port peripheral, you would wire directly from the DIPSWITCH interface component to that port input.

If, for example, you wanted to control 8 bits of a 32-bit data input, or if you wanted to use single switch signals for different device inputs, you would need to use an appropriate bus joiner device.

For more information on the available bus joiner components available for use in an FPGA design, see the Functional Classes - Bus Joiner section of the FPGA Generic Library Guide.

 

 

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