NB2DSK01 - System JTAG Programming Port

Frozen Content

The NB2DSK01 provides a dedicated host programming port, which is used to load updated NanoBoard firmware directly into the Xilinx Platform Flash Configuration PROM.


Figure 1. Update firmware using the
dedicated Host Programming Port.

The 10-pin male header caters for both Hard JTAG (pins 1-4) and Soft JTAG (pins 5-8) signals. Pin 9 of the header is tied to ground. Pin 10 is connected to the motherboard's 5V supply, via a 350mA fuse and 3A/40V Schottky diode.

Connection to the port is made from the USB port of the PC on which Altium Designer is installed. Altium's USB JTAG Adapter is used to convert the USB cabling to 10-way IDC JTAG cabling.

Location on Board

The header, labeled 'SYSTEM JTAG' (and designated HDR3) is located on the solder side of the board, at the left-hand edge and below the 'AUDIO TEST' jack.

The 350mA fuse (designated F5) and Schottky diode (designated D11) are also located on the solder-side of the board, to the bottom-left of the host programming port.

Schematic Reference

The circuitry relating to the host programming port can be found on the following sheets of the motherboard schematics:

  • Sheet 24 (JTAG_ALTIUM_HOST.SchDoc, entitled Host JTAG Header)
  • Sheet 25 (CON_HOSTJTAG_10WBOXHDRRAM.SchDoc, entitled Host JTAG Header)
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