NB2DSK01 - System Clocks

Frozen Content

Modified by Admin on Sep 13, 2017

The NB2DSK01 has an SPI-based system clock generator (an ICS307-02 device) that provides a fixed 20MHz clock and a user-programmable clock providing frequencies from 6 to 200 MHz. Both clocks are made available to the NanoTalk Controller (Xilinx Spartan-3 FPGA) and the daughter board FPGA, connected to FPGA GCLK pins.

Figure 1. NanoBoard clock circuitry
(fixed and programmable clocks).

The user-programmable clock has a default frequency of 50 MHz. It can be programmed in one of three ways:

From a PC with Altium Designer using the Instrument panel for the NanoTalk Controller. This allows frequency presets to common values, as well as any frequency possible with the ICS clock device.

Directly from the TFT LCD panel, through the firmware-driven GUI.

By the daughter board FPGA application at run time, via the NanoTalk Controller-to-daughter board SPI interconnect.

Location on Board

The ICS307-02 device (designated U3) is located on the solder side of the board, along with the 20MHz surface mount crystal (designated Y2) which is used to provide the fixed reference frequency.

In addition, two test points are made available on the component side of the board for verification of the programmable clock frequency (labeled 'FPGA CLK' and designated TP4) and fixed 20MHz frequency (labeled 'REF CLK' and designated TP3) respectively. These are located beneath the 20K trim pot (VR1) used to provide contrast control for the TFT LCD panel.

Figure 2. Fixed and
programmable clock
test points.

Schematic Reference

The system clock circuitry can be found on Sheet 35 (CLK_ICS307-02_PLL.SchDoc, entitled Programmable SPI Clock) of the motherboard schematics.

Design Interface Component

Table 1 summarizes the available design interface components that can be placed from the FPGA NB2DSK01 Port-Plugin.IntLib, to access these resources.

Table 1. System clock port-plugin components.

Component Symbol	Component Name	Description
	`CLOCK_BOARD`	Place this component to bring the NB2DSK01's programmable system clock signal into your FPGA design.
	`CLOCK_REFERENCE`	Place this component to bring the NB2DSK01's fixed 20MHz system clock signal into your FPGA design.
	`CLOCK_SUPPLY`	Place this component to bring both fixed and programmable system clock signals into your FPGA design, using a single port component.

Component Symbol

Component Name

Description

CLOCK_BOARD

Place this component to bring the NB2DSK01's programmable system clock signal into your FPGA design.

CLOCK_REFERENCE

Place this component to bring the NB2DSK01's fixed 20MHz system clock signal into your FPGA design.

CLOCK_SUPPLY

Place this component to bring both fixed and programmable system clock signals into your FPGA design, using a single port component.

The programmable clock signal (CLK_BOARD) will typically be used as the CLK_I input to devices in a design. Some peripheral devices used within a design may require input clocks of a particular frequency. This frequency is typically achieved by passing one of the system clocks through one or more clock divider devices.

For more information on the available fixed and programmable clock divider components available for use in an FPGA design, see the Generic Logic - Clock Divider section of the FPGA Generic Library Guide.

Further Device Information

For more information on the programmable ICS307-02 device, refer to the datasheet (ics3070102[1].pdf) available at www.idt.com.