NB2DSK01 - Debug Headers

Frozen Content

Modified by Admin on Sep 13, 2017

A total of 16 spare I/O pins on the NanoTalk Controller FPGA are brought out to two 10-pin headers, 8 wired to each (pins 1-8). Pin 9 of each header is tied to ground. Pin 10 is connected to the motherboard's 5V supply, via a 350mA fuse and 3A/40V Schottky diode.

Figure 1. Reserved debug headers.

These headers – and the I/O signals they convey – are reserved and not available for general use.

Location on Board

The two headers (designated DH1 and DH2 respectively) are located on the solder side, at the left-hand edge of the board.

The 350mA fuse (designated F3) and Schottky diode (designated D9) associated with debug header DH1 are located to the right of the header itself.

The 350mA fuse (designated F4) and Schottky diode (designated D10) associated with debug header DH2 are located above the header itself.

Schematic Reference

The debug header circuitry can be found on Sheet 43 (CON_DEBUG_10WBOXHDRRAM.SchDoc, entitled 8-Way Debug Header) of the motherboard schematics.