NB2DSK01 - Daughter Board Test-Reset Button

The NB2DSK01 provides a push button switch that is wired to an I/O pin of the daughter board FPGA. The button has no intrinsic function – it is simply a switch made available for FPGA design purposes. It is typically used to provide the external reset signal (RST_I) for the FPGA design. As such, it is labeled on the board as 'DAUGHTER BD TEST/RESET'.

The switch is of type SPNO – Single Pole Normally Open. In the open position, it provides a logical High signal to the daughter board FPGA, changing to logical Low when pressed.

Location on Board

The switch (designated SW8) is located on the component side of the board, to the left of 'User Header A'.

Schematic Reference

The switch circuitry can be found on Sheet 56 (SW_RESET_SPNO.SchDoc, entitled Push Button SPNO Switch) of the motherboard schematics.

Design Interface Component

Table 1 summarizes the available design interface component that can be placed from the FPGA NB2DSK01 Port-Plugin.IntLib, to access and use the push button switch, SW8.

As the signal is normally High (switch open) and the RST_I signal is active High, an inverter is typically placed directly in front of the interface component (within the FPGA design), therefore preventing a permanent reset signal.

For more information on the inverter and other generic components available for use in an FPGA design, see the FPGA Generic Library Guide.