LFECP33E-3FN672C - Supported Differential IO Standards

Frozen Content

Modified by Admin on Sep 13, 2017

The following table lists the differential I/O standards supported by the LFECP33E-3FN672C device.

Table 1. Supported differential I/O standards.

I/O Standard	Description
BLVDS	Bus Low-Voltage Differential Signaling (2.5V)
Differential HSTL15 Class I	Differential High-Speed Transceiver Logic (1.5V) Class I
Differential HSTL15 Class III	Differential High-Speed Transceiver Logic (1.5V) Class III
Differential HSTL18 Class I	Differential High-Speed Transceiver Logic (1.8V) Class I
Differential HSTL18 Class II	Differential High-Speed Transceiver Logic (1.8V) Class II
Differential HSTL18 Class III	Differential High-Speed Transceiver Logic (1.8V) Class III
Differential SSTL18 Class I	Differential Stub Series Terminated Logic (1.8V) Class I
Differential SSTL2 Class I	Differential Stub Series Terminated Logic (2.5V) Class I
Differential SSTL2 Class II	Differential Stub Series Terminated Logic (2.5V) Class II
Differential SSTL3 Class I	Differential Stub Series Terminated Logic (3.3V) Class I
Differential SSTL3 Class II	Differential Stub Series Terminated Logic (3.3V) Class II
LVDS	Low-Voltage Differential Signaling (2.5V)
LVPECL	Low-Voltage Positive Emitter-Coupled Logic (3.3V)
RSDS	Reduced Swing Differential Signaling (2.5V)

For detailed information, refer to the LatticeECP/EC Family Handbook (HB1000.pdf) available at www.latticesemi.com.