LFECP33E-3FN672C - Feature Summary
Figure 1. LatticeECP FPGA (LFECP33E-3FN672C).
The LFECP33E-3FN672C device is a member of the 1.2V ECP family of FPGAs. The ECP provides a low-cost, high-density solution for applications such as those targeted to the consumer electronics industry.
The entire ECP family includes five devices offering densities ranging from 6,100 to 32,800 LUTs. The LFECP33E-3FN672C offers 32,800 LUTs. Table 1 provides an information summary for this device.
In order to use the ECP device, you will need to install the relevant Vendor tools – Lattice® ispLever® from www.latticesemi.com. The ispLever Starter software can be downloaded but does require a license. Check the website for licensing options.
| Feature | Description |
|---|---|
Device Name | LFECP33E-3FN672C |
Vendor | Lattice |
Family | ECP |
Package | 672-Ball Fine Pitch Ball Grid Array (fpBGA672) - Lead Free |
Speed Grade | 3 |
Temperature Grade | Commercial |
Pin Count | 672 |
Maximum User I/O Pins | 496 |
Max. Differential I/O Pairs | 248 |
LUTs | 32.8K |
Embedded (Block) RAM | 498K bits (over 54 blocks) |
Distributed RAM | 131K bits |
DSP Blocks | 8 |
Embedded Multipliers | 64 (9x9); 32 (18x18); 8 (36x36) |
Clock Managers (PLLs) | 4 |
Global Clock Resources | 4 |
Configuration Memory Required | 8,089,600 bits |
On-Chip Termination Support | No |
Location on Board
The ECP device (designated U1) is located on the component side and in the lower half of the board.
Schematic Reference
The ECP device and related circuitry can be found on the following sheets of the daughter board schematics:
DEVICES.SchDoc(entitled FPGA, LEDs and SRAM Memory)
FPGA.SchDoc(entitled FPGA Connections)
FPGA_NonIO.SchDoc(entitled FPGA Power and Programming)
Bypass_FPGA_1V2.SchDoc(entitled FPGA Bypass Capacitors for 1V2)
Bypass_FPGA_3V3.SchDoc(entitled FPGA Bypass Capacitors for 3V3).
Further Device Information
For more information on the LFECP33E-3FN672C device, refer to the LatticeECP/EC Family Handbook (HB1000.pdf) available at www.latticesemi.com.