JTAG Chains in the System

Frozen Content

When a design is created and downloaded to the physical FPGA device – resident on the daughter board currently plugged into the NanoBoard – several JTAG chains are created to facilitate communications between the various devices within the system. Within Altium Designer, interaction with these chains is performed through a Devices view (Figure 1), accessed by choosing a command from the View » Devices Views sub-menu.

Figure 1. Various JTAG chains presented in Altium Designer's Devices view.

The Devices view presents three JTAG chains, which collectively show all JTAG-compliant devices attached to the system. Each device in each chain is represented by its appropriate icon. Controls for a device can be accessed through interaction (double-click, right-click) with its icon, giving full control over all JTAG devices in the system.

The following sections take a closer look at the three chains presented in the Devices view.

The NanoBoard Chain

The NanoBoard chain (Figure 2) includes an icon for each powered-up NanoBoard detected by the system. This chain essentially detects the presence of each NanoBoard's controller device, or NanoTalk Controller. As a result it is often referred to as the NanoBoard Controllers chain.

Controls associated with each icon allow you to communicate and control various on-board SPI-based devices, such as the programmable clock and the SPI Flash memory.

Figure 2. The NanoBoard chain.

The Hard Devices Chain

The Hard Devices chain (Figure 2) shows all target programmable devices detected by the system. This includes FPGAs resident on daughter board plug-ins, as well as all JTAG devices found on any user boards connected to a NanoBoard in the configuration. Any discrete processors will also be presented in this chain.

The NanoTalk Controller automatically detects and configures appropriate devices so that they form a continuous chain using their physical TDIand TDOJTAG lines. If a physical device (typically on a user board) is not supported by the system, it will appear in the chain as a Generic JTAG device. To ensure continuity of the Hard JTAG chain, a corresponding Boundary Scan Description Language(BSDL) file must be attached to the device, the contents of which are used by the system to correctly configure the JTAG chain. Should no BSDL file be available, the correct instruction length for the device can be set, ensuring JTAG chain continuity and communications with remaining devices in the chain.

Each physical device in the chain that is programmable from Altium Designer will have a Process Flow associated to it. The stages in this flow are used to interactively compile, synthesize, build and ultimately program the device, all from within the Devices view.

Figure 3. The Hard Devices chain.

The Soft Devices Chain

The Soft Devices chain (Figure 4) shows all Nexus-enabled devices, such as 'soft' processors and virtual instruments, found in each FPGA design project targeting a programmable device in the Hard Devices chain. When you use Nexus components in your design at the schematic level, the system automatically connects the TDI and TDO lines of each component's JTAG port, to form a continuous JTAG chain.

Figure 4. The Soft Devices chain.

Note: The Soft Devices chain only becomes populated with the Nexus-enabled devices for a design, once that design has been processed and downloaded into the physical FPGA device.

See Also

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